Interrupt Routing; Table 15. Pci And Pci-X* Interrupt Routing/Sharing - Intel S3210SHLX - Entry Server Board Motherboard Specification

Functional Architecture
3.4.1.2 PCI Interface for Video subsystem
The server board graphics subsystem is connected to the Intel
3.4.2

Interrupt Routing

The board interrupt architecture accommodates both PC-compatible PIC mode and APIC mode
interrupts through use of the integrated I/O APICs in the Intel
3.4.2.1 Legacy Interrupt Routing
For PC-compatible mode, the Intel
The two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary
interrupt controller (standard PC configuration). A single interrupt signal is presented to the
processor, to which the processor will respond for servicing. The Intel
configuration registers that define which interrupt source logically maps to I/O APIC INTx pins.
®
The Intel ICH9R handles both PCI and IRQ interrupts. The Intel
APIC bus. The numbers in the table below indicate the Intel
which the associated device interrupt (INTA, INTB, INTC, INTD, INTE, INTF, INTG, INTH for
PCI bus and PXIRQ0, PXIRQ1, PXIRQ2, PXIRQ3 for PCI-X bus) is connected. The Intel
ICH9R I/O APIC exists on the I/O APIC bus with the processor.
Interrupt
®
Intel 82541PI LAN (NIC2)
Integrated BMC
PCI Slot 1 (PCI 32bit/33MHz)
PCI Slot 2 (PCI 32bit/33MHz)
PCI-X* Slot 5 (64bit/133MHz) (LX board SKU
only)
PCI-X* Slot 6 (64bit/133MHz) (Riser, LX board
SKU only)
3.4.2.2 APIC Interrupt Routing
For APIC mode, the server board interrupt architecture incorporates three Intel
devices to manage and broadcast interrupts to local APICs in each processor. The Intel
APICs monitor each interrupt on each PCI device; including PCI slots in addition to the ISA
compatibility interrupts IRQ (0-15).
When an interrupt occurs, a message corresponding to the interrupt is sent across a three-wire
serial interface to the local APICs. The APIC bus minimizes interrupt latency time for
compatibility interrupt sources. The I/O APICs can also supply greater than 16 interrupt levels to
the processor(s). This APIC bus consists of an APIC clock and two bidirectional data lines.
32
®
ICH9R provides two 82C59-compatible interrupt controllers.

Table 15. PCI AND PCI-X* Interrupt Routing/Sharing

PIRQB
PIRQC
PIRQG
PIRQF
PXIRQ5
PXIRQ0
Intel® Server Boards S3200SH/S3210SH TPS
®
ICH9R via a PCIe* x1 bus.
®
ICH9R.
®
ICH9R translates these to the
®
ICH9R PCI interrupt input pin to
INT A INT B
PIRQF
PIRQG
PXIRQ6
PXIRQ1
®
ICH9R contains
®
INT C INT D
PIRQE PIRQH
PIRQH PIRQE
PXIRQ7 PXIRQ4
PXIRQ2 PXIRQ3
®
I/O APIC
®
Revision 1.3
I/O