Intel SE7520AF2 Technical Product Specification page 31

Intel® Server Board SE7520AF2 TPS
3.1.1.1 Front Side Bus (FSB)
The Intel® E7520 MCH supports either single or dual processor configurations using the Intel®
Xeon™ processor with 1 MB L2 cache or the Intel® Xeon™ processor with 2 MB L2 cache. The
MCH supports a base system bus frequency of 200 MHz. The address and request interface is
double pumped to 400 MHz while the 64-bit data interface (+ parity) is quad pumped to
800 MHz. This provides a matched system bus address and data bandwidths of 6.4 GB/s.
3.1.1.2 MCH Memory Sub-System Overview
The MCH provides an integrated memory controller for direct connection to two channels of
registered DDR2 400 MHz memory (stacked or unstacked). Peak theoretical memory data
bandwidth using DDR2 400 MHz technology is 6.4 GB/s.
When both memory channels are populated and operating, they function in lock-step mode. On
the Intel® Server Board SE7520AF2, the maximum supported DDR2 400 MHz memory
configuration is 16 GB.
The Intel® E7520 MCH memory interface provides several RASUM (Reliability, Availability,
Serviceability, Usability and Manageability) features, including:
Memory mirroring that allows for two copies of all data in the memory subsystem (one on
each channel) to be maintained.
Memory sparing that allows for one DIMM per channel to be held in reserve and brought
on-line if another DIMM in the channel becomes defective. DIMM sparing and memory
mirroring are mutually exclusive of one another.
Hardware periodic memory scrubbing, including demand scrub support.
Retry on uncorrectable memory errors.
Intel® x4 Single Device Data Correction (SDDC) for memory error detection and
correction of any number of bit failures in a single x4 memory device.
3.1.1.3 PCI Express* Interface
The Intel® E7520 MCH is the first Intel chipset to support the new PCI Express* high-speed
serial I/O interface for superior I/O bandwidth. The scalable PCI Express* interface of the MCH
complies with the PCI Express Interface Specification, Rev 1.0a.
The MCH provides three x8 PCI Express* interfaces, each with a max theoretical bandwidth of
4.2GB/s. Each of these x8 PCI Express* interfaces may alternatively be configured as two
independent x4 PCI Express* interfaces. A PCI Express* interface/port is defined as a collection
of lanes. Each lane (x1) consists of two striped differential pairs in each direction (transmit and
receive). The raw bit-rate on the data pins of 2.5 Gb/s, results in a real bandwidth per pair of
250MB/s given the 8/10 bit encoding used to transmit data across this interface.
The Intel® E7520 MCH is a root class component as defined in the PCI Express Interface
Specification. The PCI Express* interfaces of the MCH support connection to a variety of
bridges and devices compliant with the same revision of the specification.
Revision 1.2
Intel order number C77866-003
Functional Architecture
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