Intel SE7525RP2 Technical Manual
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Intel SE7525RP2 Technical Manual

Technical product specification
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Intel® Server Board
SE7320EP2 / Intel® Server
Board SE7525RP2
Technical Product Specification
Intel order number D24635-001
Revision 1.0
April 29, 2005
Enterprise Platforms and Services Division - Marketing

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Summary of Contents for Intel SE7525RP2

  • Page 1 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 Technical Product Specification Intel order number D24635-001 Revision 1.0 April 29, 2005 Enterprise Platforms and Services Division - Marketing...

  • Page 2: Revision History

    Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 3: Table Of Contents

    Table of Contents 1. Introduction ........................11 Server Board Use Disclaimer ................11 2. Intel® Server Board SE7320EP2 / SE7525RP2 Overview ..........12 Intel® Server Boards SE7320EP2 and SE7525RP2 Feature Set ......12 3. Functional Architecture ..................... 14 Processor and Memory Subsystem ............... 14 3.1.1...
  • Page 4 Table of Contents Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 5.4.2 APIC Interrupt Routing................... 37 5.4.3 Serialized IRQ Support ..................38 PCI Error Handling....................40 6. BIOS............................. 41 BIOS Architecture ....................41 6.1.1 BIOS Identification String..................41 System Initialization ....................42 6.2.1...
  • Page 5 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 Table of Contents 7. Hardware and System Management ................. 82 Hardware Management ..................82 7.1.1 Fan Speed Control Diagram .................. 82 7.1.2 Chassis Intrusion ....................83 Intel® Server Management (ISM) Software Support ..........83 Additional System Management Components............
  • Page 6 Table of Contents Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 9.4.6 "POST Error Pause" option.................. 103 10. Server Board SE7320EP2 and SE7525RP2 Connectors ..........104 10.1 Main Power Connector ..................104 10.2 Memory Module Connector ................. 105 10.3 Processor Socket....................
  • Page 7 Figure 3. Memory Sub-system Block Diagram................17 Figure 4. Memory Bank Label Definition..................19 Figure 5. Intel® Server Boards SE7320EP2 and SE7525RP2 SMBUS Block Diagram ..... 28 Figure 6. Intel® Server Boards SE7320EP2 and SE7525RP2 Clock Distribution Diagram ..30 Figure 7.
  • Page 8 List of Tables Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 List of Tables Table 1. Processor Support Matrix ..................... 14 Table 2. Memory Bank Labels ....................18 Table 3. I C Addresses for Memory Module SMB ..............19 Table 4.
  • Page 9 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 List of Tables Table 33. BIOS Setup, PCI Configuration Sub-menu Selections ..........67 Table 34. BIOS Setup, Memory Configuration Sub-menu Selections......... 68 Table 35. BIOS Setup, Boot Menu Selections ................69 Table 36.
  • Page 10 List of Tables Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 Table 68. Power Connector Pin-out (J12)................. 104 Table 69. Auxiliary Signal Connector (J5)................. 104 Table 70. Auxiliary CPU Power Connector Pin-out (J22) ............105 Table 71. DIMM Connectors (J16,J18,J20,J21) ............... 105 Table 72.

  • Page 11: Introduction

    Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the...

  • Page 12: Intel® Server Board Se7320Ep2 / Se7525Rp2 Overview

    Intel Server Board SE7525RP2 also meets the needs of a high-end workstation system. The architecture is based around the Intel® E7320/E7525 chipset and is capable of supporting one or two Intel® Xeon™ processors with 1MB or 2MB L2 cache and up to 8GB of memory. Intel® Server Boards SE7320EP2 and SE7525RP2 Feature Set...

  • Page 13: Figure 1. Block Diagram Of Intel® Server Boards Se7320Ep2 And Se7525Rp2

    SSI-compliant connectors for SSI interface support: front panel and power connectors The following figure below shows the functional blocks of the server boards and the plug-in modules that they support. Figure 1. Block Diagram of Intel® Server Boards SE7320EP2 and SE7525RP2 Revision 1.0 Intel order number D24635-001...

  • Page 14: Functional Architecture

    Intel® Server Boards SE7320EP2 and SE7525RP2. Processor and Memory Subsystem The Intel® chipset E7320 / E7525 provides a 36-bit address, 64-bit data processor host bus interface, operating at 800 MHz in the AGTL+ signaling environment. The MCH component of...
  • Page 15 3.1.1.1 Processor VRD The Intel Server Boards SE7320EP2 and SE7525RP2 have two Voltage Regulator Downs (VRDs) to support two processors. This is compliant with the VRM 10.1 specification and provides a maximum of 210 Amps, which is capable of supporting the requirements for two Intel®...

  • Page 16: Figure 2. Cek 'Passive' Component Stackup

    3.1.1.5 Common Enabling Kit (CEK) Design Support The server boards have been designed to comply with the Intel® Common Enabling Kit (CEK) processor mounting and thermal solution. The server boards ship from Intel’s factory with a CEK spring snapped onto the underside of the board, beneath each processor socket. The CEK spring is removable to allow the use of non-Intel heat sink retention solutions.

  • Page 17: Memory Subsystem

    The board supports DDR2-400 compliant ECC DIMMS operating at 400MT/s. Only DIMMs tested and qualified by Intel or a designated memory test vendor are supported on this board. All DIMMs are supported by design, but only fully qualified DIMMs will be supported on the board.

  • Page 18: Table 2. Memory Bank Labels

    For designs that require a lower price point, a single 256MB DIMM can be populated in the DIMM 1B socket. When a single DIMM is installed, interleaving and Intel x4 SDDC are not available. Bank 2 will only operate with two DIMMs installed.

  • Page 19: Figure 4. Memory Bank Label Definition

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Functional Architecture Bank 1 Bank 2 Figure 4. Memory Bank Label Definition 3.1.2.3 C Bus The I C bus is used by the system BIOS to retrieve DIMM information needed to program the MCH memory registers, which are required to boot the system.

  • Page 20: Intel® E7320 / E7525 Chipset

    The ECC used for DRAM provides Intel® x4 SDDC technology for x4 SDRAMs. DRAMs that are x8 use the same algorithm but will not have Intel x4 SDDC technology, since at most only four bits can be corrected with this ECC.

  • Page 21: Mch Memory Architecture Overview

    It uses seventeen address lines (BA [2:0] and MA [13:0]) and supports 256 Mb, 512 Mb, 1 Gb DRAM densities. The DDR2 DIMM interface supports memory scrubbing, single- bit error correction, and multiple bit error detection and Intel x4 SDDC with x4 DIMMs. 3.2.1.1...

  • Page 22: Memory Controller Hub (Mch)

    The MCH is a 1077-ball FC-BGA device and uses the proven components of previous generations like the Intel® Xeon™ processor bus interface unit, the hub interface unit, and the DDR2 memory interface unit. In addition, the MCH incorporates a PCI Express interface. The PCI Express interface allows the MCH to directly interface with the PXH/PXHD or PCI Express devices.
  • Page 23 I/O transfers and bus master IDE transfers. The 6300ESB ICH supports two IDE channels, supporting two drives each (drives 0 and 1). The Intel Server Boards SE7320EP2 and SE7525RP2 implement one 40-pin IDE connector to access the IDE functionality.

  • Page 24: Table 5. 6300Esb Ich Gpio Usage Table

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Functional Architecture 3.2.3.7 APIC The 6300ESB ICH integrates an I/O APIC capability with 24 interrupts. 3.2.3.8 General Purpose Input and Output Pins The 6300ESB ICH provides a number of general purpose input and output pins. Many of these pins have alternate functions, and thus all are not available.

  • Page 25: Super I/O

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Functional Architecture Pin Name (Powe GPI / GPO / Signal Name Function Description Well) Function GPIO39 Core Input/Output DIS_VGA_N Output: Active Low to disable on board VGA GPIO40 Core Input/Output...

  • Page 26: Gpios

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Functional Architecture 3.3.1 GPIOs The Super I/O provides a number of general-purpose input/output pins that the server boards utilize. The following table identifies the pin and the signal name used in the schematics: Table 6.

  • Page 27: Serial Ports

    The Super I/O contains functionality that allows various events to control the power-on and power-off the system. BIOS Flash The board incorporates an Intel® FWH flash memory component. The 82802AC is a high- performance 8-megabit memory component and non-volatile storage space. The flash device is connected through the LPC interface of 6300ESB.

  • Page 28: Sm Bus Block Diagram

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Functional Architecture SM Bus Block Diagram See below for the SM Bus block diagram and device addresses. Figure 5. Intel® Server Boards SE7320EP2 and SE7525RP2 SMBUS Block Diagram Revision 1.0 Intel order number D24635-001...

  • Page 29: Clock Generation And Distribution

    Clock Generation and Distribution Clock Generation and Distribution All buses on the Intel Server Boards SE7320EP2 / SE7525RP2 operate using synchronous clocks. Clock synthesizer/driver circuitry on the server board generates clock frequencies and voltage levels as required, including the following: 200 MHz at 0.7V current-mode: For processor 0, processor 1, debug port and MCH...

  • Page 30: Figure 6. Intel® Server Boards Se7320Ep2 And Se7525Rp2 Clock Distribution Diagram

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Clock Generation and Distribution Figure 6. Intel® Server Boards SE7320EP2 and SE7525RP2 Clock Distribution Diagram Revision 1.0 Intel order number D24635-001...

  • Page 31: Pci I/O Subsystem

    PCI I/O Subsystem PCI Subsystem The primary I/O buses for the server boards SE7320EP2 and SE7525RP2 are PCI, PCI Express, and PCI-X, with three independent PCI bus segments. The PCI buses comply with the PCI Local Bus Specification, Revision 2.3. The P32-A bus and the P64-B segment are directed through the 6300ESB ICH and the two PCI Express (x4 and x16) buses are directed through the MCH.

  • Page 32: P64-B 66-Mhz Pci-X Subsystem

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS PCI I/O Subsystem 5.1.1.2 P32-A Arbitration P32-A supports four PCI devices: the 6300ESB ICH and four PCI bus masters (one NIC, two PCI slots, and one ATI* Rage* XL video controller). All PCI masters must arbitrate for PCI access, using resources supplied by the 6300ESB ICH.

  • Page 33: Pci Express X8

    5.1.3 PCI Express x8 The PCI Express x8 interface can be configured as two independent x4 interfaces. On the Intel Server Boards SE7320EP2 and SE7525RP2, Lanes 0-3 are connected to a x8 PCI Express connector and Lane 4 is connected to Marvell 88E8050. Lanes 5-7 are terminated.

  • Page 34: Video Controller

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS PCI I/O Subsystem Video Controller The server boards provide an ATI Rage XL PCI graphics accelerator, along with 8MB of video SDRAM and support circuitry for an embedded SVGA video subsystem. The ATI Rage XL chip contains a SVGA video controller, clock generator, 2D and 3D engine, and RAMDAC in a 272- pin PBGA.

  • Page 35: Video Memory Interface

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS PCI I/O Subsystem 5.2.2 Video Memory Interface The memory controller subsystem of the ATI Rage XL arbitrates requests from direct memory interface, the VGA graphics controller, the drawing coprocessor, the display controller, the video scalar, and hardware cursor.

  • Page 36: Network Interface Controller (Nic)

    The server boards SE7320EP2 and SE7525RP2 support one 10Base-T / 100Base / 1000Base- T network interface controller (NIC) based on the Intel® 82541PI controller (NIC 2) and one gigabit network interface controller based on the Marvell* 88E8050 controller (NIC 1).

  • Page 37: Apic Interrupt Routing

    For APIC mode, the interrupt architecture incorporates three Intel I/O APIC devices to manage and broadcast interrupts to local APICs in each processor. The Intel I/O APICs monitor each interrupt on each PCI device, including PCI slots, in addition to the ISA compatibility interrupts IRQ(0-15).

  • Page 38: Serialized Irq Support

    5.4.3 Serialized IRQ Support The Server Boards SE7320EP2 and SE7525RP2 supports a serialized interrupt delivery mechanism. Serialized Interrupt Requests (SERIRQ) consists of a start frame, a minimum of 17 IRQ / data channels, and a stop frame. Any slave device in the quiet mode may initiate the start frame.

  • Page 39: Figure 9. Interrupt Routing Diagram

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS PCI I/O Subsystem Super I/O Timer Keyboard Cascade Serial Port2/ISA SERIRQ SERIRQ Serial Port1/ISA Floppy/ISA SCI/ISA Mouse/ISA Coprocessor Error P IDE/ISA Not Used 82541PI INTA PIRQA# PIRQB# Video INTA, Slot 3 INTC, Slot 5 INTB...

  • Page 40: Pci Error Handling

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS PCI I/O Subsystem PCI Error Handling The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry the offending transaction, or to report it using SERR#.

  • Page 41: Bios

    The Basic Input/Output System (BIOS) is implemented as firmware that resides in the Flash ROM. It provides hardware-specific initialization algorithms and standard PC-compatible basic input/output (I/O) services, and standard Intel® Server Board features. The Flash ROM also contains firmware for certain embedded devices. These images are supplied by the device manufacturers and are not specified in this document.

  • Page 42: System Initialization

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS System Initialization 6.2.1 Processors 6.2.1.1 Multiple Processor Initialization IA-32 processors have a microcode-based bootstrap processor (BSP) arbitration protocol. On reset, all of the processors compete to become the BSP. If a serious error is detected during a Built-in Self-Test (BIST), that processor does not participate in the initialization protocol.
  • Page 43 6.2.1.6 Jumperless Processor Speed Settings The Intel® Xeon™ processor does not use jumpers or switches to set the processor frequency. The BIOS reads the highest ratio register from all processors in the system. If all processors are the same speed, the Actual Ratio register is programmed with the value read from the High Ratio register.
  • Page 44 6.2.1.11.2 Activating and Deactivating Intel® EM64T The BIOS does not activate Intel® EM64T mode. The system will be in IA-32 compatibility mode when booting an operating system. If the operating system and/or applications are detected to be 64-bit capable, then the processor will automatically configure itself for 64-bit operation, otherwise it will remain in 32-bit execution mode.

  • Page 45: Memory Subsystem

    For double-sided DIMMs, both rows are said to be present. The Server Boards SE7320EP2 and SE7525RP2 have four DIMM slots, or two DIMM banks. Both DIMMs in a bank should be identical (same manufacturer, CAS latency, number of rows, columns and devices, timing parameters etc.).
  • Page 46 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS The BIOS reads the Serial Presence Detect (SPD) SEEPROMs on each installed memory module to determine the size and timing of the installed memory modules. The memory-sizing algorithm determines the size of each bank of DIMMs. The BIOS programs the memory controller in the chipset accordingly.

  • Page 47: Table 18. Supported Ddr2-400 Dimm Populations

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS DDR2-400 DIMM population rules are as follows: DIMMs banks must be populated in order starting with the slots furthest from MCH Dual rank DIMMs must be populated before single rank DIMMs...

  • Page 48: Table 20. Memory Error Handling In Non-Ras Mode

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.2.2.5.2 Memory Error Handling in non-RAS Mode If memory RAS features are not enabled in BIOS Setup, BIOS will apply “10 SBE errors in one hour” implementation. Enabling of this implementation and RAS features are mutually-exclusive and automatically handled by system BIOS.
  • Page 49 6.2.2.7.2 Integrated Memory Scrub Engine The Intel E7320/ E7525 MCH includes an integrated engine to walk the populated memory space proactively seeking out soft errors in the memory subsystem. In the case of a single bit correctable error, this hardware detects and corrects the data except when an incoming write to the same memory address is detected.
  • Page 50 DIMMs will be visible in normal address space. Note: The Server Boards SE7320EP2 and SE7525RP2 do not support the memory sparing for dual-rank DDR2 RAM. DIMM Sparing feature requires that the spare DIMM be at least the size of the largest primary DIMM in use.

  • Page 51: Pci

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS Hardware additions for this feature include the implementation of tracking register per DIMM to maintain a history of error occurrence, and a programmable register to hold the fail-over error threshold level.

  • Page 52: Pci Express

    6.2.4.1 PCI Express Initialization The Intel® Server Board SE7525RP2 includes one X4 slot and one X16 slot. The Intel® Server Board SE7320EP2 includes one x4 slot. The BIOS trains the link during boot and checks the corresponding status to disable any port not connected to PCI Express devices.

  • Page 53: Keyboard/Mouse

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.2.4.2 PCI Express Enhanced Configuration Mechanisms PCI Express extends the configuration space to 4096 bytes per device/function as compared to the 256 bytes allowed by the PCI 2.3 configuration space. The PCI Express configuration space is divided into a PCI 2.3 compatible region and an extended PCI Express region.

  • Page 54: Flash Rom

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.2.9 Flash ROM The BIOS supports a 1MB flash part. The flash ROM contains system initialization routines, setup utility, and runtime support routines. A 64KB block is available for storing OEM code (user binary) and custom logos.

  • Page 55: System Diagnostic Screen

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.3.1.2 Logo/Diagnostic Window The middle portion of the screen is reserved for the Logo/Diagnostic Window. On a graphics console, the window is 640x384. On a text console, the window is 80x20.

  • Page 56: Bios Boot Popup Menu

    <Esc> key while in Quiet Boot mode. If Quiet Boot is disabled, the BIOS displays diagnostic messages in place of the activity indicator and the splash screen. With the use of an Intel supplied utility, the BIOS allows OEMs to override the standard Intel logo with one of their own design.

  • Page 57: Console Redirection

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.4.2 Console Redirection The BIOS Setup utility is functional via console redirection over various terminal standards emulation. This may limit some functionality for compatibility, e.g., usage of colors or some keys or key sequences or support of pointing devices.

  • Page 58: Entering Bios Setup

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS Option Description Setup Defaults Pressing <F9> causes the following to appear: Load Setup Defaults? [OK] [Cancel] If “OK” is selected and the <Enter> key is pressed, all setup fields are set to their default values.

  • Page 59: Table 24. Bios Setup, Advanced Menu Options

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS Feature Options Help Text Description System Memory Size Amount of physical memory detected Server Board MCH Stepping Stepping Display stepping revision of the Memory Controller. System Time HH:MM:SS Use [ENTER], [TAB] or [SHIFT- Configures the system time on a 24 TAB] to select a field.

  • Page 60: Table 25. Bios Setup, Processor Configuration Sub-Menu Options

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.4.5.2.1 Processor Configuration Sub-menu Table 25. BIOS Setup, Processor Configuration Sub-menu Options Feature Options Help Text Description Configure Advanced Processor Settings Manufacturer Intel Displays processor manufacturer string Brand String...

  • Page 61: Table 26. Bios Setup Ide Configuration Menu Options

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS Feature Options Help Text Description Adjacent Cache Line This option enables / disables Disabled Prefetch the processor Adjacent Cache Enabled Line Prefetch Feature. Changing the default may affect performance depending on the application being used.
  • Page 62 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS Feature Options Help Text Description Mixed PATA / SATA Lets you remove a PATA and Selects submenu for configuring replace it by SATA in a given mixed PATA and SATA.

  • Page 63: Table 27. Mixed Pata-Sata Configuration With Only Primary Pata

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS Table 27. Mixed PATA-SATA Configuration with only Primary PATA Feature Options Help Text Description Mixed PATA / SATA First ATA Configure this channel to PATA or Defines the SATA device for...

  • Page 64: Table 29. Bios Setup, Floppy Configuration Sub-Menu Selections

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS Feature Options Help Text Description PIO Mode Select PIO Mode. The Auto setting is correct in most Auto cases. DMA Mode Select DMA Mode. The Auto setting is correct in most Auto cases.

  • Page 65: Table 30. Bios Setup, Super I/O Configuration Sub-Menu

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.4.5.2.4 Super I/O Configuration Sub-menu Table 30. BIOS Setup, Super I/O Configuration Sub-menu Feature Options Help Text Description Configure National Semiconductor* 42x Super I/O Chipset Serial Port A Address...

  • Page 66: Table 32. Bios Setup, Usb Mass Storage Device Configuration Sub-Menu Selections

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS Feature Options Help Text Description USB Configuration USB Devices List of USB Enabled devices detected by BIOS. USB Function Disabled Enables USB HOST controllers. When set to disabled, other...

  • Page 67: Table 33. Bios Setup, Pci Configuration Sub-Menu Selections

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS Feature Options Help Text Description Device #n Only displayed if a device is detected, includes a DeviceID string returned by the USB device. Emulation Type If Auto, USB devices less than 530MB will be Auto emulated as floppy and remaining as hard drive.

  • Page 68: Table 34. Bios Setup, Memory Configuration Sub-Menu Selections

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.4.5.2.7 Memory Configuration Sub-menu This sub-menu provides information about the DIMMs detected by the BIOS. The DIMM number is printed on the server boards next to each device. Table 34. BIOS Setup, Memory Configuration Sub-menu Selections...

  • Page 69: Table 35. Bios Setup, Boot Menu Selections

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.4.5.3 Boot Menu Table 35. BIOS Setup, Boot Menu Selections Feature Options Help Text Description Boot Settings Boot Settings Configuration Configure settings during system boot. Selects submenu. Boot Device Priority Specifies the boot device priority sequence.

  • Page 70: Table 37. Bios Setup, Boot Device Priority Sub-Menu Selections

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.4.5.3.2 Boot Device Priority Sub-menu Selections Table 37. BIOS Setup, Boot Device Priority Sub-menu Selections Feature Options Help Text Description Boot Device Priority 1st Boot Device Varies Specifies the boot sequence from the Number of entries will vary based on available devices.

  • Page 71: Table 40. Bios Setup, Cd/Dvd Drives Sub-Menu Selections

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.4.5.3.2.3 ATAPI CDROM drives sub-menu selections Table 40. BIOS Setup, CD/DVD Drives Sub-menu Selections Feature Options Help Text Description CD/DVD Drives 1st Drive Varies Specifies the boot sequence from the available Varies based on system configuration.

  • Page 72: Table 42. Bios Setup, Server Menu Selections

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.4.5.5 Server Menu Table 42. BIOS Setup, Server Menu Selections Feature Options Help Text Description System management Selects submenu. Serial Console Features Selects submenu. Event Log configuration Configures event logging.

  • Page 73: Table 44. Bios Setup, Serial Console Features Sub-Menu Selections

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.4.5.5.2 Serial Console Features Sub-menu Selections Table 44. BIOS Setup, Serial Console Features Sub-menu Selections Feature Options Help Text Description Serial Console Features BIOS Redirection Port If enabled, BIOS uses the specified serial...

  • Page 74: Table 45. Bios Setup, Event Log Configuration Sub-Menu Selections

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.4.5.5.3 Event Log Configuration Sub-menu Selections Table 45. BIOS Setup, Event Log Configuration Sub-menu Selections Feature Options Help Text Description Event Log Configuration View Event Log View all unread events on the Event Log.

  • Page 75: Security

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS Security The BIOS provides a number of security features. This section describes the security features and operating model. The BIOS uses passwords to prevent unauthorized tampering with the server. Once secure mode is entered, access to the server is allowed only after the correct password(s) has been entered.

  • Page 76: Administrator/User Passwords And F2 Setup Usage Model

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.5.2 Administrator/User Passwords and F2 Setup Usage Model Notes: Visible = option string is active and changeable Hidden = option string is inactive and not visible Shaded = option string is gray-out and view-only...

  • Page 77: Password Clear Jumper

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS Scenario #3 Administrator Password Is Installed User Password Is Not Installed Login Type: Supervisor Set Admin Password (visible) Set User Password (visible) User Access Level [(show current status of user access level)] (visible) Clear User Password (shaded) Login Type: <Enter>...

  • Page 78: Flash Architecture And Flash Update Utility

    The flash ROM contains system initialization routines, the BIOS Setup Utility, and runtime support routines. The exact layout is subject to change, as determined by Intel. A 64KB user block is available for user ROM code or custom logos. The flash ROM also contains initialization code in compressed form for onboard peripherals, such as NIC and video controllers.
  • Page 79 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.6.1.1.1 Updating the BIOS from DOS 1. Make sure that the flash bootable disk contains both the ROM image and the afudos update utility. 2. Boot to DOS. 3. Run the afudos utility as follows: AFUDOS /i<ROM filename>...

  • Page 80: Update Oem Logo

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.6.1.2.1 BIOS Recovery The BIOS has a ROM image size of 1MB. The BIOS is made up of a boot block recovery section, a main BIOS section, an OEM logo/user binary section, and an NVRAM section.
  • Page 81 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS BIOS 6.6.2.2 Changing the OEM Logo for Microsoft* Windows* 2000 / 2003 / XP 1. Boot to Microsoft Windows 2000 / 2003 / XP. 2. Download OEMLOGO.exe, Rombuild.exe, RomFile, and NewOEMlogoImage to the hard drive.

  • Page 82: Hardware And System Management

    Hardware and System Management Hardware Management The Intel Server Boards SE7320EP2 and SE7525RP2 have an integrated National Semiconductor* Heceta 6 (LM96000) controller that is responsible for hardware monitoring. The Heceta 6 controller provides basic server hardware monitoring which alerts a system administrator if a hardware problem occurs on the board.

  • Page 83: Chassis Intrusion

    Intel® Server Management (ISM) Software Support The Server Boards SE7320EP2 and SE7525RP2 have been designed to work with the Intel® Server Management (ISM) software version 8.x. For additional information on this software and its interaction with the server boards, see the Intel Server Management 8.x Technical Product...

  • Page 84: Wired For Management (Wfm)

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Hardware and System Management 7.3.2 Wired For Management (WFM) Wired for Management (WMF) is an industry-wide initiative that increases the overall manageability and reduces the total cost of ownership. WFM allows a server to be managed over a network.

  • Page 85: Sleep Support

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Sleep Support Sleep Support The BIOS supports forced boots from: PXE, HDD, FDD, and CD. On each boot, the BIOS determines what changes to boot options have been set by invoking the Get System Boot Options command, takes appropriate action, and clears these settings.

  • Page 86: Sleep And Wake Functionality

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Sleep Support While entering the S4 state, the operating system saves the context to the disk and most of the system is powered off. The system can wake on a power button press, or a signal received from a wake-on-LAN compliant LAN card (or onboard LAN), modem ring, PCI power management interrupt, or RTC alarm.

  • Page 87: On To Sleep (Acpi)

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Sleep Support 8.2.4 On to Sleep (ACPI) If an operating system is loaded, the operating system retains control of the system and operating system policy determines into which sleep state the system transitions.

  • Page 88: Error Logging

    The error codes are defined by Intel and whenever possible are backward compatible with error codes used on earlier platforms.

  • Page 89: Processor Bus Error

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging 9.2.2 Processor Bus Error If the chipset supports ECC on the processor bus, the BIOS enables the error correction and detection capabilities of the processors by setting appropriate bits in the processor model specific register (MSR) and appropriate bits inside the chipset.

  • Page 90: Table 50. Post Code Checkpoints

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging 9.4.1.2 POST Code Checkpoints The following table describes the type of checkpoints that may occur during the POST portion of the BIOS. Table 50. POST Code Checkpoints Checkpoint Description Disable NMI, Parity, video for EGA, and DMA controllers.
  • Page 91 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging Checkpoint Description Test for total memory installed in the system. Also, Check for DEL or <Esc> keys to limit memory test. Display total memory in the system. Mid POST initialization of chipset registers.

  • Page 92: Table 51. Boot Block Initialization Code Checkpoints

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging 9.4.1.3 Boot Block Initialization Code Checkpoints The boot block initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the boot block initialization.

  • Page 93: Table 52. Boot Block Recovery Code Checkpoints

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging 9.4.1.4 Boot Block Recovery Code Checkpoints The boot block recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the boot block recovery portion of the BIOS.

  • Page 94: Table 53. Dim Code Checkpoints

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging 9.4.1.5 DIM Code Checkpoints The Device Initialization Manager (DIM) gets control at various times during BIOS POST to initialize different system buses. The following table describes the main checkpoints where the DIM module is accessed.

  • Page 95: Bios Messages

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging The lower nibble 'Y' indicates the bus on which the different routines are being executed. 'Y' can be from 0 to 5. 0 = Generic DIM (Device Initialization Manager).

  • Page 96: Table 57. Storage Device Bios Messages

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging Message Displayed Description Drive Not Ready The BIOS was unable to access the drive because it indicated it was not ready for data transfer. This is often reported by drives when no media is present.
  • Page 97 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging Message Displayed Description 5th Slave Hard Disk Error The IDE/ATAPI device configured as Slave in the 5th IDE controller could not be properly initialized by the BIOS. This message is typically displayed when the BIOS is trying to detect and configure IDE/ATAPI devices in POST.

  • Page 98: Table 58. Virus Related Bios Messages

    Microcode Error BIOS could not find or load the CPU Microcode Update to the CPU. This message only applies to INTEL CPUs. The message is most likely to appear when a brand new CPU is installed in a motherboard with an outdated BIOS.

  • Page 99: Table 60. Cmos Bios Messages

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging Message Displayed Description Static Resource Conflict Two or more Static Devices are trying to use the same resource space (usually Memory or I/O). PCI I/O conflict A PCI adapter generated an I/O resource conflict when configured by BIOS POST.

  • Page 100: Post Error Messages And Handling

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging Table 62. USB BIOS Error Messages Message Displayed Description Warning! Unsupported USB device found and disabled! This message is displayed when a non-bootable USB device is enumerated and disabled by the BIOS.

  • Page 101: Table 64. Post Error Messages And Handling

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging Table 64. POST Error Messages and Handling Error Code Error Message Response 0000 Timer Error Pause 0003 CMOS Battery Low Pause 0004 CMOS Settings Wrong Pause 0005 CMOS Checksum Bad...

  • Page 102: Boot Block Error Beep Codes

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging Error Code Error Message Response 0180 BIOS does not support current stepping – P0 Pause 0181 BIOS does not support current stepping – P1 Pause 0192 L2 cache size mismatch...

  • Page 103: Post Error Beep Codes

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Error Logging 9.4.5 POST Error Beep Codes The following table lists the POST error beep codes. Prior to system video initialization, the BIOS uses these beep codes to inform users of error conditions.

  • Page 104: Server Board Se7320Ep2 And Se7525Rp2 Connectors

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors 10. Server Board SE7320EP2 and SE7525RP2 Connectors 10.1 Main Power Connector The main power supply connection is obtained using the 24-pin connector. The following table defines the pin-outs of the connector.

  • Page 105: 10.2 Memory Module Connector

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors Table 70. Auxiliary CPU Power Connector Pin-out (J22) Signal 18 AWG color Signal 18 AWG Color Black +12V1 White Black 12V1 RS Yellow (24AWG)
  • Page 106 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors Front Side (left 1 - 60) Back Side (right 121-180) Front Side (left 61 - 120) Back Side (right 181-240) Non- Pin # Non-...

  • Page 107: 10.3 Processor Socket

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors 10.3 Processor Socket The board has two Socket 604 processor sockets. The following table provides the processor socket pin numbers and pin names: Table 72. Socket 604 Processor Socket Pin-out (J36, J37)
  • Page 108 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name BPM0# AC11 D43# A21#...
  • Page 109 Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name THERMDA AD24 D21# DEFER#...

  • Page 110: I C Header

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors 10.4 I C Header Table 73. HSBP Header Pin-out (J30,J54) Signal Name Description HR_SMB_P5V_DAT Data Line GROUND HR_SMB_P5V_CLK Clock Line Pull-up for J30 Pull-down for J54 Table 74.

  • Page 111: 10.5 Pci Slot Connector

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors 10.5 PCI Slot Connector There are three PCI buses implemented on the server boards. PCI segment A supports 5V 32-bit/33MHz PCI, segment B supports 3.3V 64-bit/66MHz PCI-X, and segment C supports 3.3V PCI Express operation.

  • Page 112: Table 76. P64-B 3.3V 64-Bit/66-Mhz Pci-X Slot Pin-Out (J8, J9)

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors Table 76. P64-B 3.3V 64-bit/66-MHz PCI-X Slot Pin-out (J8, J9) Side B Side A Side B Side A -12V TRST# M66EN AD[09] +12V MODE2...

  • Page 113: Table 77. Pci Express Slot Pin-Out (J13 For X8, J14 For X16)

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors Side B Side A Side B Side A C/BE[1]# AD[15] AD[33] Ground AD[14] +3.3V Ground AD[32] Ground AD[13] Reserved Reserved AD[12] AD[11] Reserved Ground...

  • Page 114: 10.6 Front Panel Connector

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors Side B Side A Side B Side A End of the x4 connector HSOP4 RSVD HSOP14 HSON4 HSON14 HSIP4 HSIP14 HSIN4 HSIN14 HSOP5 HSOP15...

  • Page 115: 10.7 Vga Connector

    DDCDAT DDCCLK Note: NC (No Connect) 10.8 NIC Connector The Server Boards SE7320EP2 and SE7525RP2 supports two NIC RJ45 connectors. The following table details the pin-out of the connector. Table 80. NIC1-82541PI(10/100/1000) Connector Pin-out (JA1,JA2) Signal Name Signal Name Power...

  • Page 116: 10.9 Ide Connector

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors 10.9 IDE Connector The board provides one 40-pin ATA-100 IDE connectors Table 81. ATA 40-pin Connector Pin-out (J43) Signal Name Signal Name RESET# IDE_DD7...

  • Page 117: 10.11 Usb Connector

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors 10.11 USB Connector The following table provides the pin-out for the dual external USB connectors. This connector is at the rear I/O area. Table 83. USB Connectors Pin-out (J55)

  • Page 118: 10.12 Floppy Connector

    FDSKCHG# 10.13 Serial Port Connector Two serial ports are provided on the Server Boards SE7320EP2 and SE7525RP2. A standard, external DB9 serial connector is located on the back edge of the server boards to supply a Serial A interface. And this connector is combined with VGA connector (J4) A Serial B port is provided through a 9-pin header (J15) on the server boards.

  • Page 119: 10.14 Keyboard And Mouse Connector

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors 10.14 Keyboard and Mouse Connector Two PS/2 ports are provided for use by a keyboard and a mouse. The following table details the pin-out of the PS/2 connectors.

  • Page 120: Intrusion Cable Connector

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors Table 90. 6-pin Fan Headers Pin-out (J50) Signal Name Type Description PWM Input Ground Power GROUND is the power supply ground Fan Power Power...

  • Page 121: Table 92. System Recovery And Update Jumper Options

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Server Board SE7320EP2 and SE7525RP2 Connectors The following table describes each jumper option. Table 92. System Recovery and Update Jumper Options Function Pin – Pin Function Description CMOS CLEAR These three pins are connected to GPIs of Super I/O.

  • Page 122: 11. General Specifications

    11.2 Mean Time Between Failure (MTBF) Intel has calculated the MTBF for the Server Boards SE7320EP2 and SE7525RP2 as follows: Table 94. MTBF Calculation Ambient Temperature MTBF Calculation 55°...

  • Page 123: 11.3 Processor Power Support

    EMTS values will supersede these, and should be used. 11.4 Power Supply Specifications This section provides power supply design guidelines for a system using either the Intel Server Boards SE7320EP2 or SE7525RP2, including voltage and current specifications, and power supply on/off sequencing characteristics.

  • Page 124: Figure 13. Output Voltage Timing

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS General Specifications Figure 13 shows the output voltage timing parameters. Vout 10% Vout vout rise vout_off vout_on Figure 13. Output Voltage Timing The following tables show the timing requirements for a single power supply being turned on and off via the AC input, with PSON held low and the PSON signal, with the AC input applied.

  • Page 125: Table 98. Turn On / Off Timing

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS General Specifications Table 98. Turn On / Off Timing Item Description Units Tsb_on_delay Delay from AC being applied to 5VSB being within regulation. 1500 msec T ac_on_delay Delay from AC being applied to all output voltages being within...

  • Page 126: Voltage Recovery Timing Specifications

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS General Specifications AC Input vout_holdup Vout pwok_low AC_on_delay pwok_off sb_on_delay pwok_on sb_on_delay pwok_off pwok_on PWOK pson_pwok pwok_holdup 5VSB sb_vout pson_on_delay PSON AC turn on/off cycle PSON turn on/off cycle Figure 14. Turn On / Turn Off Timing 11.4.2...

  • Page 127: Table 99. Transient Load Requirements

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS General Specifications Table 99. Transient Load Requirements Output Step Load Size Load Slew Rate Capacity Load +3.3 V 7.0 A 0.25 A/ s 4700 F +5 V 7.0 A 0.25 A/ s...

  • Page 128: 12. Product Regulatory Compliance

    12.1.1 Product EMC Compliance The Intel Server Board SE7320EP2 and SE7525RP2 has been tested and verified to comply with the following electromagnetic compatibility (EMC) regulations when installed in a compatible Intel host system. For information on compatible host system(s), contact your local Intel representative.

  • Page 129: Mandatory/Standard: Certifications, Registration, Declarations

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Product Regulatory Compliance 12.1.2 Mandatory/Standard: Certifications, Registration, Declarations UL Recognition (US/Canada) CE Declaration of Conformity (CENELEC Europe) FCC/ICES-003 Class A Verification (USA/Canada) VCCI Certification (Japan) – Verification Only C-Tick Declaration of Conformity (Australia)

  • Page 130: Ministry Of Economic Development (New Zealand) Declaration Of Conformity

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Product Regulatory Compliance 12.2.3 Ministry of Economic Development (New Zealand) Declaration of Conformity This product has been tested to AS/NZS 3548, and complies with New Zealand’s Ministry of Economic Development emission requirements.

  • Page 131: Appendix A: Integration And Usage Tips

    Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips This section provides a bullet list of useful information that is unique to the Intel® Server Board SE7320EP2 and Intel Server Board SE7525RP2 and should be kept in mind while assembling and configuring a system based on either of these boards.

  • Page 132: Glossary

    Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS Glossary Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “AGP 4x”).

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