Interrupt Routing; Legacy Interrupt Routing; Table 6. Pci Interrupt Routing/Sharing - Intel SE7500CW2 Technical Product Specification

SE7500CW2 Server Board Technical Product Specification
•
4 pin header for off board LEDs
Pin-out for the card is as follows:
Table 6. Optional Intel® 53C1000B1 SCSI card pin-out(J1)
Pin
1
2
3
4
4.5

Interrupt Routing

The SE7500CW2 interrupt architecture accommodates both PC-compatible PIC mode and
APIC mode interrupts through use of the integrated I/O APICs in the ICH3-S.
4.5.1

Legacy Interrupt Routing

For PC-compatible mode, the ICH3-S provides two 82C59-compatible interrupt controllers. The
two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary interrupt
controller (standard PC configuration). A single interrupt signal is presented to the processors, to
which only one processor will respond for servicing. The ICH3-S contains configuration registers
that define which interrupt source logically maps to I/O APIC INTx pins.
Interrupts, both PCI and IRQ types, are handled by the ICH3-S. The ICH3-S then translates these
to the APIC bus. The numbers in the table below indicate the ICH3-S PCI interrupt input pin to
which the associated device interrupt (INTA, INTB, INTC, INTD) is connected. The ICH3-S' I/O
APIC exists on the I/O APIC bus with the processors.
Interrupt
ATI Rage SL
Promise ATA-100 Controller
82550PM #2
82550PM #1
P64H2 BT INTR#
P64-C Slot 1
P64-B Slot 2
P64-B Slot 3
P32-A Slot 4
P32-A Slot 5
21
Revision 1.40
Signal Name
+5V
LED1_L
LED1_L
+5V
Table 7. PCI Interrupt Routing/Sharing
INT A INT B
ICH3_PIRQF_L
ICH3_PIRQG_L
ICH3_PIRQE_L
ICH3_PIRQH_L
ICH3_PIRQC# (for PIC mode)
P1_IRQ0_L P1_IRQ1_L
P2_IRQ0_L P2_IRQ1_L
P2_IRQ4_L P2_IRQ5_L
ICH3_PIRQB_L ICH3_PIRQC_L
ICH3_PIRQD_L ICH3_PIRQA_L
Included PCI Devices
INT C INT D
P1_IRQ2_L P1_IRQ3_L
P2_IRQ2_L P2_IRQ3_L
P2_IRQ6_L P2_IRQ7_L
ICH3_PIRQB_L ICH3_PIRQC_L
ICH3_PIRQD_L ICH3_PIRQA_L