Intel SE7525GP2 Technical Manual
  1. Manuals
  2. Brands
  3. Intel Manuals
  4. Server Board
  5. SE7525GP2
  6. Technical manual

Intel SE7525GP2 Technical Manual

Technical product specification
Hide thumbs Also See for SE7525GP2:
Table of Contents

Advertisement

Quick Links

See also: User Manual
®
Intel
Server Boards
SE7320SP2 and SE7525GP2
Technical Product Specification
Intel reference number D24635-004
Revision 4.0
December, 2005
Enterprise Platforms and Services Division - Marketing

Advertisement

Table of Contents
loading

Related Manuals for Intel SE7525GP2

Summary of Contents for Intel SE7525GP2

  • Page 1 ® Intel Server Boards SE7320SP2 and SE7525GP2 Technical Product Specification Intel reference number D24635-004 Revision 4.0 December, 2005 Enterprise Platforms and Services Division - Marketing...

  • Page 2: Revision History

    Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice.

  • Page 3: Table Of Contents

    Server Board SE7320SP2 Feature Set............2 ® Intel Server Board SE7525GP2 ................4 ® 2.2.1 Intel Server Board SE7525GP2 Feature Set ............4 3. Functional Architecture ....................... 8 Processor Sub-system..................... 9 3.1.1 Processor Voltage Regulator Devices (VRDs) ............10 3.1.2 Reset Configuration Logic ..................10 3.1.3...
  • Page 4 Contents Intel® Server Boards SE7320SP2 and SE7525GP2 3.4.7 Universal Serial Bus (USB) Controller ..............21 3.4.8 RTC ........................21 3.4.9 GPIO........................21 3.4.10 Enhanced Power Management ................22 3.4.11 System Management Bus (SMBus 2.0)..............22 Memory Sub-System ..................... 22 3.5.1 Memory Sizing .......................
  • Page 5 Intel® Server Boards SE7320SP2 and SE7525GP2 Contents 4.3.3 Configuration Reset ....................60 4.3.4 Keyboard Commands .................... 61 Entering BIOS Setup ..................... 62 4.4.1 Main Menu ......................62 4.4.2 Advanced Menu..................... 63 4.4.3 Boot Menu ......................73 4.4.4 Security Menu......................75 4.4.5...
  • Page 6 Contents Intel® Server Boards SE7320SP2 and SE7525GP2 5.1.4 Private Management Buses................... 98 5.1.5 Mini-Baseboard Management Controller ............... 99 Onboard Platform Instrumentation Features and Functionality ......101 5.2.1 mBMC Self-test....................102 5.2.2 SMBus Interfaces ....................102 5.2.3 External Interface to mBMC................. 102 5.2.4...
  • Page 7 Intel® Server Boards SE7320SP2 and SE7525GP2 Contents Checkpoints ......................133 6.3.1 System ROM BIOS POST Task Test Point (Port 80h Code)....... 133 6.3.2 Diagnostic LEDs ....................133 6.3.3 POST Code Checkpoints..................135 6.3.4 Bootblock Initialization Code Checkpoints............137 6.3.5 Bootblock Recovery Code Checkpoint ..............138 6.3.6...
  • Page 8 Contents Intel® Server Boards SE7320SP2 and SE7525GP2 Processor Power Support..................162 Power Supply Specifications ................162 8.4.1 Power Timing....................... 162 8.4.2 Voltage Recovery Timing Specifications ............. 166 9. Product Regulatory Compliance..................167 Product Safety Compliance ................. 167 9.1.1 Product EMC Compliance ................... 167 9.1.2...
  • Page 9 Server Board SE7320SP2 Layout Reference ............4 ® Table 2. Intel Server Board SE7525GP2 Layout Reference ............7 Table 3. Processor Support Matrix ..................... 12 Table 4. Supported DDR-266 DIMM Populations ............... 24 Table 5. Supported DDR-333 DIMM Populations ............... 25 Table 6.
  • Page 10 Contents Intel® Server Boards SE7320SP2 and SE7525GP2 Table 23. BIOS Setup, Advanced Menu Options................ 63 Table 24. BIOS Setup, Processor Configuration Sub-menu Options ......... 63 Table 25. BIOS Setup IDE Configuration Menu Options ............65 Table 26. Mixed PATA-SATA Configuration with only Primary PATA ........66 Table 27.
  • Page 11 Intel® Server Boards SE7320SP2 and SE7525GP2 Contents Table 58. Built-in Platform Sensors ..................122 Table 59. External Platform Sensors ..................123 Table 60. POST Error Messages and Handling................ 129 Table 61. Boot Block Error Beep Codes ................... 132 Table 62. POST Error Beep Codes ..................132 Table 63.
  • Page 12 Contents Intel® Server Boards SE7320SP2 and SE7525GP2 Table 93. Three-pin Fan Headers Pin-out (J51, J52, J7, J1, J45, J48) ........157 Table 94. Six-pin Fan headers Pin-out (J44, J46) ..............158 Table 95. Intrusion Cable Connector (J19) Pin-out..............158 Table 96. SCSI LED Header Pin-out (J26) ................158 Table 97.

  • Page 13: Introduction

    Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the...

  • Page 14: Server Board Overview

    The Server Board SE7525GP2 has features that also make it suitable for the workstation market. The features of both boards will be discussed in detail in this document. Unless otherwise noted, features discussed in this document apply to both server boards.

  • Page 15: Figure 1. Intel Server Board Se7320Sp2 Layout

    Intel® Server Boards SE7320SP2 and SE7525GP2 Server Board Overview ® The following figure shows the board layout of the Intel Server Board SE7320SP2. Each connector and major component is identified by number and identified in Table 1. ® Figure 1. Intel Server Board SE7320SP2 Layout Revision 4.0...

  • Page 16: Intel ® Server Board Se7525Gp2

    Intel Server Board SE7525GP2 One SKU of the Server Board SE7525GP2 is available. This section describes its feature set. While similar to the Server Board SE7320SP2, there are specific features that make this server board suitable for an entry-level workstation solution as well as an entry-server environment.
  • Page 17 Light-Guided Diagnostics on most FRU devices (processors, memory) Port-80 diagnostic LEDs displaying POST Codes ® The following figure shows the board layout of the Intel Server Board SE7525GP2. Each connector and major component is identified by number and identified in Table 2.

  • Page 18: Figure 2. Intel Server Board Se7525Gp2 Layout

    Server Board Overview Intel® Server Boards SE7320SP2 and SE7525GP2 ® Figure 2. Intel Server Board SE7525GP2 Layout Revision 4.0...

  • Page 19: Table 2. Intel Server Board Se7525Gp2 Layout Reference

    Intel® Server Boards SE7320SP2 and SE7525GP2 Server Board Overview ® Table 2. Intel Server Board SE7525GP2 Layout Reference Ref # Description Ref # Description Processor sockets Front panel header DIMM connectors (from left to right PATA HDD connectors (primary = blue,...

  • Page 20: Functional Architecture

    Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture This chapter provides a high-level description of the functionality associated with the architectural blocks that make up the server boards. Note: Due to the similarities between these two products, this chapter discusses all features that are present on both products.

  • Page 21: Processor Sub-System

    Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture ® Figure 4. Intel Server Board SE7525GP2 Block Diagram Processor Sub-system The support circuitry for the processor sub-system consists of the following: Dual 604-pin zero insertion force (ZIF) processor sockets Processor host bus AGTL+ support circuitry...

  • Page 22: Processor Voltage Regulator Devices (Vrds)

    FMB is an estimation of the maximum values the 800-MHz FSB versions of the Intel Xeon processors will have over their lifetime. The value is only an estimate and actual specifications for future processors may differ. At present, the current demand per FMB is a sustained maximum of a 105 amps and peak support of 120 amps.

  • Page 23: Common Enabling Kit (Cek) Design Support

    3.1.5 Common Enabling Kit (CEK) Design Support The server board has been designed to comply with Intel’s common enabling kit (CEK) processor mounting and heatsink retention solution. The server board will ship with a CEK spring snapped onto the underside of the board, beneath each processor socket. The CEK spring is removable, allowing for the use of non-Intel heatsink retention solutions.

  • Page 24: Processor Support

    Xeon processors utilizing an 800 MHz front side bus with frequencies starting at 2.8 GHz. Previous generations of Intel Xeon processors are not supported on either of these server boards. The server board is designed to provide current up to 120 A per processors. Processors with higher current requirements are not supported.
  • Page 25 3.1.6.7 Microcode IA-32 processors have the capability of correcting specific errata through the loading of an Intel supplied data block, i.e., microcode update. The BIOS is responsible for storing the update in non-volatile memory and loading it into each processor during POST. The BIOS allows a number of microcode updates to be stored in the flash, limited by the amount of free space available.

  • Page 26: Multiple Processor Initialization

    3.1.6.12 Execute Disable Bit support ® ® The system BIOS supports the execute-disable (NX) bit in the latest Intel Xeon processors. This option can be enabled or disabled in the BIOS setup utility. It is disabled by default to allow users to opt-in to the protection this feature provides.

  • Page 27: Cpu Thermal Sensors

    3.1.10 Processor Thermal Trip Shutdown ® ® If a thermal overload condition exists (thermal trip) an Intel Xeon processor outputs a digital signal that is monitored by the server board management sub-system. A thermal trip is a critical condition and indicates that the processor may become damaged if it continues to run. To help protect the processor, the management controller automatically powers off the system.

  • Page 28: Memory Controller Hub (Mch)

    Front Side Bus (FSB) ® ® The Intel E7320 MCH supports either single- or dual-processor configurations using Intel ® Xeon processors designed for the 800 MHz system bus. The MCH supports a base system bus frequency of 200 MHz. The address and request interface is double pumped to 400 MHz while the 64-bit data interface (+ parity) is quad pumped to 800 MHz.

  • Page 29: Intel E7525 Chipset (Intel Server Board Se7525Gp2)

    ® The Intel E7320 MCH is part of the first family of Intel chipsets to support the PCI Express* high speed serial I/O interface for high I/O bandwidth. The Intel E7320 MCH implementation of the scalable PCI Express interface complies with the PCI Express Interface Specification, Rev 1.0a.

  • Page 30: Memory Controller Hub (Mch)

    Intel E7525 MCH, the maximum supported memory size at DDR266, DDR333 or DDR2-400 is 12 GB. On the Server Board SE7525GP2, the maximum supported memory size at DDR266 or DDR333 is 8 GB. DDR2-400 memory is not supported on this server board.

  • Page 31: Intel ® 6300Esb Ich

    ® The Intel E7525 MCH is part of the first family of Intel chipsets to support the PCI Express* high speed serial I/O interface for high I/O bandwidth. The Intel E7525 MCH implementation of the scalable PCI Express interface complies with the PCI Express Interface Specification, Rev 1.0a.

  • Page 32: Pci Interface

    The bus is also PCI 2.2 compliant to provide backwards compatibility with PCI devices. The Intel 6300ESB ICH also works as the PCI arbiter on this bus and supports up to four external PCI bus masters in addition to the Intel 6300ESB I/O controller. Two 3.3V PCI-X connectors are on this bus.

  • Page 33: Advanced Programmable Interrupt Controller (Apic)

    14 external and two internal interrupts are possible. In addition, the Intel 6300ESB I/O controller supports a serial interrupt scheme. All of the registers in these modules can be read and restored. This is required to save and restore the system state after power has been removed and restored to the platform.

  • Page 34: Enhanced Power Management

    I2C commands are implemented. The Intel 6300ESB I/O controller SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). Also, the Intel 6300ESB I/O controller supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command,...

  • Page 35: Memory Population

    3.5.2 Memory Population The mixing of memory DDR266 and DDR333 is supported on Server Board SE7320SP2 and Server Board SE7525GP2. However, when mixing DIMM speeds, DDR333 will be treated as DDR266. DIMM search rules for standard mode: 1. If DIMM dual pair# >= 1, set memory controller to dual-channel mode. Otherwise, go to step 2.

  • Page 36: Figure 6. Dimm Socket Configuration

    Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 The following diagram identifies the memory bank locations on the server board. Figure 6. DIMM Socket Configuration The following tables show supported memory populations. Table identifiers: S/R = single rank D/R = dual rank E = Empty Table 4.

  • Page 37: I 2 C Bus

    Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture Table 5. Supported DDR-333 DIMM Populations DIMM Slot A2 DIMM Slot A1 DIMM Slot B2 DIMM Slot B1 Table 6. DIMM Module Capacities Parts 128Mb 256Mb 512Mb X8, single row 256 MB...

  • Page 38: Disabling Dimms

    The expected error rates for DIMMs are stated per gigabyte of memory. This information comes from three sources: Intel experimental measurements (one and one-half errors per year) Data from a memory component vendor (one error per month) The results from a 10-year study by a major computer manufacturer (four errors per...

  • Page 39: Memory Rasum Features

    Memory RASUM Features ® The Intel E7320 MCH and Intel E7525 MCH support several memory RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) features that have traditionally been found only on high end server systems. These features include x4 SDDC for memory error detection and correction, Memory Scrubbing, Retry on Correctable Errors, Integrated Memory Initialization, and DIMM Sparing.
  • Page 40 ® The Intel E7320 and Intel E7525 MCHs include an integrated engine to walk the populated memory space proactively seeking out soft errors in the memory subsystem. In the case of a single bit correctable error, this hardware detects, logs, and corrects the data except when an incoming write to the same memory address is detected.
  • Page 41 ® The Intel E7320 and Intel E7525 MCHs provide hardware managed ECC auto-initialization of all populated DRAM space under software control. Once internal configuration has been updated to reflect the types and sizes of populated DIMM devices, the MCH will traverse the populated address space initializing all locations with good ECC.

  • Page 42: I/O Sub-System

    Express4) bus segment controlled from the MCH on the Intel Server Board SE7320SP2 is available. Or one x4 PCI Express bus segment and one x16 PCI Express bus segment (P64- Express16) are available on the Intel Server Board SE7525GP2. The table below lists the characteristics of the different PCI bus segments.
  • Page 43 3.6.1.4 P64-Express16: x16 PCI Express bus segment ® Intel Server Board SE7525GP2 only: The P64-Express16 bus segment supports x16 PCI Express signaling. 3.6.1.5 Scan Order The BIOS assigns PCI bus numbers in a depth-first hierarchy, in accordance with the PCI Local Bus Specification.

  • Page 44: Split Option Rom

    6300ESB I/O controller contains configuration registers that define which interrupt source logically maps to I/O APIC INTx pins. Interrupts, both PCI and IRQ types, are handled by the Intel 6300ESB I/O controller. The Intel 6300ESB I/O controller then translates these to the APIC bus. The numbers in the table below indicate the Intel 6300ESB I/O controller PCI interrupt input pin to which the associated device interrupt (INTA, INTB, INTC, INTD) is connected.

  • Page 45: Table 12. Interrupt Definitions

    The IRQ / data frame structure includes the ability to handle up to 32 sampling channels with the standard implementation using the minimum 17 sampling channels. The server boards have an external PCI interrupt serializer for PCI IRQ scan mechanism of Intel 6300ESB I/O controller to support 16 PCI IRQs.

  • Page 46: Figure 7. Interrupt Routing (Intel ® 6300Esb Internal)

    Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 6300ESB ICH I/O APIC HI1.5 INTERFACE IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 6300ESB IRQ10 6300ESB IRQ11 IRQ12 IRQ13 8259PIC IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22...

  • Page 47: Figure 8. Interrupt Routing

    Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture Super I/O Timer Keyboard Cascade Serial Port2/ISA SERIRQ SERIRQ Serial Port1/ISA Floppy/ISA SCI/ISA Mouse/ISA Coprocessor Error P IDE/ISA Not Used Intel 82541 INTA PIRQA# PIRQB# Video INTA, Slot 3 INTC, Slot 5 INTB...

  • Page 48: Ide Support

    SATA ports on the server board. The SATA ports can be enabled/disabled and/or configured by accessing the BIOS Setup Utility during POST. The SATA function in the Intel 6300ESB I/O controller has dual modes of operation to support different operating system conditions. In the case of Native IDE enabled operating systems, the Intel 6300ESB I/O controller has separate PCI functions for serial and parallel ATA.

  • Page 49: Video Controller

    The Intel RAID Technology for SATA Option ROM provides a pre-OS user interface for the Intel RAID Technology implementation and provides the ability for an Intel RAID Technology volume to be used as a boot disk as well as to detect any faults in the Intel RAID Technology volume(s) ®...

  • Page 50: Table 13. Video Modes

    Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 3.6.6.1 Video Modes The Rage* XL chip supports all standard IBM* VGA modes. The following table shows the 2D/3D modes supported for both CRT and LCD. Table 13. Video Modes 2D Mode...

  • Page 51: Network Interface Controller (Nic)

    Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture The server boards support an 8-MB (512 KB x 32-bit x four banks) SDRAM device for video memory. The following table shows the video memory interface signals: Table 14. Video Memory Interface...

  • Page 52: Usb 2.0 Support

    Super I/O Chip ® The Server I/O is the National Semiconductor* PC87427 controller. It is located on the Intel 6300ESB I/O controller LPC bus. For LPC and SMBus access, the PC87427features a fast X- Bus, over which boot flash and I/O devices can be accessed. The PC87427supports X-Bus address line forcing (to 0 or 1) to access two BIOS code and data sets.

  • Page 53: Table 15. Super I/O Gpio Usage Table

    GPIOs The National Semiconductor* PC87427 Super I/O provides nine general-purpose input/output pins that the SE7320SP2 and Server Board SE7525GP2 utilizes. The following table identifies the pin and the signal name used in the schematic: Table 15. Super I/O GPIO Usage Table...

  • Page 54: Table 16. Serial B Header Pin-Out

    Intel® Server Boards SE7320SP2 and SE7525GP2 3.6.9.2 Serial Ports Both the SE7320SP2 and Server Board SE7525GP2 provide two serial ports: an external DB9 Serial port, and an internal DH-10 Serial header. The following sub-sections provide details on the use of the serial ports.

  • Page 55: Bios Flash

    Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture 3.6.10 BIOS Flash ® An Intel 3-volt Advanced+ Boot Block 28F320C3 Flash memory component is used as the BIOS flash device. The 28F320C3 is a high-performance 32-megabit memory component that provides 2048 K x 16 (4 MB) of BIOS and non-volatile storage space. The flash device is connected through the X-bus from the SIO.

  • Page 56: Figure 9. Intel ® Xeon ® Processor Memory Address Space

    Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 64 GB Hi PCI Memory Address Range Upper Memory Ranges Additional Main Memory Address Range 4 GB Lo PCI Memory Space Range Top of Low Memory (TOLM) TSEG SMRAM Main Memory Address Range...

  • Page 57: Figure 10. Dos Compatibility Region

    Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture 3.7.1.1 DOS Compatibility Region The first region of memory below 1 MB was defined for early PCs, and must be maintained for compatibility reasons. The region is divided into sub-regions as shown in the following figure.
  • Page 58 Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 DOS Area The DOS region is 512 KB in the address range 0 to 07FFFFh. This region is fixed and all accesses go to main memory. ISA Window Memory The ISA Window Memory is 128 KB between the address of 080000h to 09FFFFh. This area can be mapped to the PCI bus or main memory.

  • Page 59: Figure 11 Extended Memory Map

    Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture 3.7.1.2 Extended Memory Extended memory is defined as all address space greater than 1 MB. Extended Memory region covers 8 GB maximum of address space from addresses 0100000h to FFFFFFFh, as shown in the following figure.
  • Page 60 Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 Main Memory All installed memory greater than 1 MB is mapped to local main memory, up to 8 GB of physical memory. Memory between 1 MB to 15 MB is considered to be standard ISA extended memory.

  • Page 61: Table 17. Smm Space Table

    System Management RAM (SMRAM) provides code and data storage space for the SMI_L handler code, and is made visible to the processor only on entry to SMM, or other conditions which can be configured using the Intel chipset. The MCH supports three SMM options:...

  • Page 62: I/O Map

    6300ESB I/O controller, have built-in features that support PC-compatible I/O devices and functions, which are mapped to specific addresses in I/O space. On SE7320SP2 and SE7525GP2, the Intel 6300ESB I/O controller provides the bridge to ISA functions. The I/O map in the following table shows the location in I/O space of all direct I/O-accessible registers.
  • Page 63 Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture Address (es) Resource Notes 0074h NMI Mask (bit 7) & RTC address (bits 6::0) Aliased from 0070h 0076h NMI Mask (bit 7) & RTC address (bits 6::0) Aliased from 0070h 0071h RTC Data...

  • Page 64: Accessing Configuration Space

    Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 Address (es) Resource Notes 03E8h – 03Efh Serial Port A 03F0h – 03F5h Floppy Disk Controller 03F6h – 03F7h Primary IDE – Sec Floppy 03F8h – 03FFh Serial Port A (primary) 0400h – 043Fh...

  • Page 65: Figure 12. Config_Addres Register

    Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture 3.7.3.1 CONFIG_ADDRESS Register CONFIG_ADDRESS is 32 bits wide and contains the field format shown in the following figure. Bits [23::16] choose a specific bus in the system. Bits [15::11] choose a specific device on the selected bus.
  • Page 66 Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 PCI Device IDSEL Bus# / Device# / Function# MCH EXP Bridge A1 00 / 03 / 00 MCH EXP Bridge B0 00 / 04 / 00 MCH EXP Bridge B1 00 / 05 / 00...

  • Page 67: Clock Generation And Distribution

    66 MHz at 3.3 V logic levels: For MCH and Intel 6300ESB 48 MHz at 3.3V logic levels: For Intel 6300ESB and SIO. 33 MHz at 3.3V logic levels: For Intel 6300ESB, Video, BMC and SIO. 14.318 MHz at 2.5 V logic levels: For Intel 6300ESB and video.

  • Page 68: System Bios

    System (BIOS), which is based on an AMI 8.0 core architecture. The BIOS is implemented as firmware that resides in Flash ROM. It provides hardware-specific initialization algorithms and ® standard PC-compatible basic input/output (I/O) services, and standard Intel Server Board features. The Flash ROM also contains firmware for embedded PCI devices.

  • Page 69: Bios Post Splash Screen

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS During board development, the system BIOS will have a unique BIOS ID for the sever boards. The following is a sample data string that will be displayed during POST: SE7320SP2.86B.P.05.00.0028.10072004 SE7525GP2.86B.P.05.00.0028.10072004 BIOS POST Splash Screen The BIOS supports one system splash screen.
  • Page 70 System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 4.2.1.1 System State Window The top row of the screen is reserved for the system state window. On a graphics console, the window is 640x48. On a text console, the window is 80x2.

  • Page 71: Table 20. Sample Bios Popup Menu

    <Esc> key while in Quiet Boot mode. If Quiet Boot is disabled, the BIOS displays diagnostic messages in place of the activity indicator and the splash screen. With the use of an Intel-supplied utility, the BIOS allows OEMs to override the standard Intel logo with one of their own design.

  • Page 72: Bios Setup Utility

    The BIOS Setup utility uses the Unicode standard and is capable of displaying setup forms in (EFIGS) languages currently included in the Unicode standard. The BIOS supports English, Spanish, French, German, and Italian. Intel provides translations for console strings in the supported languages. The language can be selected using BIOS user interface.

  • Page 73: Keyboard Commands

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.3.4 Keyboard Commands The Keyboard Command Bar supports the following: Table 21. BIOS Setup Keyboard Command Bar Options Option Description Enter Execute The Enter key is used to activate sub-menus when the selected feature is a sub-...

  • Page 74: Entering Bios Setup

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 Entering BIOS Setup The BIOS Setup utility is accessed by pressing the <F2> hot-key during POST. Note: Some BIOS setup options are based on latest BIOS. If your server has an older BIOS, you may see some differences.

  • Page 75: Advanced Menu

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.4.2 Advanced Menu Table 23. BIOS Setup, Advanced Menu Options Feature Options Help Text Description Advanced Settings WARNING: Setting wrong values in below sections may cause system to malfunction. Processor Configuration Configure processors.
  • Page 76 System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 Feature Options Help Text Description Cache L3 Displays cache L3 size. Visible only if the processor contains an L3 cache. Max CPUID Value Limit This should be enabled in Disabled order to boot legacy OSes...

  • Page 77: Table 25. Bios Setup Ide Configuration Menu Options

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.4.2.2 IDE Configuration Sub-menu Table 25. BIOS Setup IDE Configuration Menu Options Feature Options Help Text Description IDE Configuration Onboard PATA Disabled Disabled: disables the Controls state of integrated Channels integrated PATA controller.

  • Page 78: Table 26. Mixed Pata-Sata Configuration With Only Primary Pata

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 Feature Options Help Text Description Third IDE Master While entering setup, BIOS Selects submenu with additional auto detects the presence of device details. IDE devices. This displays the status of auto detection of IDE devices.

  • Page 79: Table 27. Bios Setup, Ide Device Configuration Sub-Menu Selections

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS Table 27. BIOS Setup, IDE Device Configuration Sub-menu Selections Feature Options Help Text Description Primary/Secondary/Third/Fourth IDE Master/Slave Device Display detected device info Vendor N/A. Display IDE device vendor. Size Display IDE DISK size.

  • Page 80: Table 28. Bios Setup, Floppy Configuration Sub-Menu Selections

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 DMA Mode Select DMA Mode. The auto setting is correct in most Auto cases. SWDMA0-0 Auto :Auto detected SWDMA :SinglewordDMAn SWDMA0-1 MWDMA :MultiwordDMAn SWDMA0-2 MWDMA0-0 UWDMA :UltraDMAn MWDMA0-1 MWDMA0-2 UWDMA0-0 UWDMA0-1 UWDMA0-2...

  • Page 81: Table 29. Bios Setup, Super I/O Configuration Sub-Menu

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.4.2.4 Super I/O Configuration Sub-menu Table 29. BIOS Setup, Super I/O Configuration Sub-menu Feature Options Help Text Description Configure National Semiconductor 42x Super I/O Chipset Serial Port A Disabled Allows BIOS to Select Serial Port A...

  • Page 82: Table 31. Bios Setup, Usb Mass Storage Device Configuration Sub-Menu Selections

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 4.4.2.6 USB Mass Storage Device Configuration Sub-menu Table 31. BIOS Setup, USB Mass Storage Device Configuration Sub-menu Selections Feature Options Help Text Description USB Mass Storage Device Configuration USB Mass Storage 10 Sec...

  • Page 83: Table 32. Bios Setup, Pci Configuration Sub-Menu Selections

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.4.2.7 PCI Configuration Sub-menu This sub-menu provides control over PCI devices and their option ROMs. If the BIOS is reporting POST error 146, use this menu to disable option ROMs that are not required to boot the system.

  • Page 84: Table 33. Bios Setup, Memory Configuration Sub-Menu Selections

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 4.4.2.8 Memory Configuration Sub-menu This sub-menu provides information about the DIMMs detected by the BIOS. The DIMM number is printed on the server board next to each device. Table 33. BIOS Setup, Memory Configuration Sub-menu Selections...

  • Page 85: Boot Menu

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.4.3 Boot Menu Table 34. BIOS Setup, Boot Menu Selections Feature Options Help Text Description Boot Settings Boot Settings Configuration Configure settings during system boot. Selects submenu. Boot Device Priority Specifies the boot device priority sequence.

  • Page 86: Table 36. Bios Setup, Boot Device Priority Sub-Menu Selections

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 4.4.3.2 Boot Device Priority Sub-menu Selections Table 36. BIOS Setup, Boot Device Priority Sub-menu Selections Feature Options Help Text Description Boot Device Priority Boot Device Varies Specifies the boot sequence from the Number of entries will vary based on available devices.

  • Page 87: Security Menu

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.4.3.2.3 ATAPI CD-ROM Drives Sub-menu Selections Table 39. BIOS Setup, CD/DVD Drives Sub-menu Selections Feature Options Help Text Description CD/DVD Drives Drive Varies Specifies the boot sequence from the available Varies based on system configuration.

  • Page 88: Server Menu

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 Secure Mode Period of key/PS/2 mouse This node is grayed out if a user 1 minute Timer inactivity specified for Secure password is not installed. 2 minutes Mode to activate. A password is...
  • Page 89 Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS Feature Options Help Text Description Resume on AC Power Determines the mode of When set to “Stays Off,” Stays Off Loss operation if a power loss occurs. “Front Panel Switch Power On Stays off, the system will remain Inhibit”...

  • Page 90: Table 42. Bios Setup, System Management Sub-Menu Selections

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 4.4.5.1 System Management Sub-menu Selections Table 42. BIOS Setup, System Management Sub-menu Selections Feature Options Help Text Description System Management Server Board Part Number Field contents varies Server Board Serial Number Field contents varies...

  • Page 91: Table 43. Bios Setup, Serial Console Features Sub-Menu Selections

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.4.5.3 Serial Console Features Sub-menu Selections Table 43. BIOS Setup, Serial Console Features Sub-menu Selections Feature Options Help Text Description Serial Console Features BIOS Redirection Port If enabled, BIOS uses the specified serial...

  • Page 92: Table 44. Bios Setup, Event Log Configuration Sub-Menu Selections

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 4.4.5.4 Event Log Configuration Sub-menu Selections Table 44. BIOS Setup, Event Log Configuration Sub-menu Selections Feature Options Help Text Description Event Log Configuration Clear All Event Logs Setting this to Enabled will clear the system...

  • Page 93: Exit Menu

    The flash ROM contains system initialization routines, the BIOS Setup Utility, and runtime support routines. The exact layout is subject to change, as determined by Intel. A 64 KB user block is available for user ROM code or custom logos. The flash ROM also contains initialization code in compressed form for onboard peripherals, like SCSI, NIC and video controllers.

  • Page 94: Flash Update Utility

    BIOS. To this end, the flash is divided into two partitions, primary and secondary. The active partition from which the system boots is referred to as the primary partition. The AMI FLASH update suite and Intel online updates preserve the existing BIOS image on the primary partition.
  • Page 95 Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS Where: /n don't check ROM ID Choose one: /pb Program Boot Block /pn Program NVRAM /pc Destroy System CMOS /r registry path to store result of operation (only for Windows version) /k Program non-critical block only...

  • Page 96: User Binary Area

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 4.7.1.4 Updating the BIOS from the EFI Shell Make sure that the flash disk contains the ROM image and the AFUEFI utility. Boot to the EFI Shell with the flash disk. Do a map -r to retrieve the file system on the disk.
  • Page 97 Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.7.3.1 BIOS Recovery The BIOS has a ROM image size of 2 MB. A standard 1.44 MB floppy diskette cannot hold the entire ROM file due to the large file size. To compensate for this, a Multi-disk recovery method is available for BIOS recover (see Section 4.7.3.2 for further details).

  • Page 98: Update Oem Logo

    A utility tool is used to change the OEM logo in ROM. The OEM logo can then be updated by flashing the ROM. For details on how to replace the logo with an OEM logo, download and follow the instructions in Customize BIOS with OEM Logo white paper available on the Intel Support website. Revision 4.0...
  • Page 99 Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS Command-line Usage: OEMLogo <RomFileName> <NewOEMImageFileName> [/F or /FN or /N] OEMLogo <RomFileName> [/D] Where [/F] forces replacement of the OEM logo even if the logo formats do not match. [/N] inserts the 16-color BMP without converting it to the default AMI format.

  • Page 100: Oem Binary

    C0000h to EFFFFh. The system vendor can place a signature within the user binary to distinguish it from other option ROMs. Intel provides the tools and reference code to help OEMs build a user binary. The user binary must adhere to the following requirements: In order to be recognized by the BIOS and protected from runtime memory managers, the user binary must have an option ROM header (55AA, size).

  • Page 101: Operating System Boot, Sleep, And Wake

    Operating System Boot, Sleep, and Wake 4.9.1 Microsoft Windows* Compatibility Intel Corporation and Microsoft Corporation co-author design guides for system designers using ® Intel processors and Microsoft* operating systems. These documents are updated yearly to address new requirements and current trends.

  • Page 102: Sleep And Wake Functionality

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 ACPI BIOS: This is the code that boots the machine and implements interfaces for sleep, wake, and some restart operations. The ACPI Description Tables are also provided by the ACPI BIOS. The BIOS supports S0, S1, S4, and S5 states. S1 and S4 are considered sleep states. The ACPI specification defines the sleep states and requires the system to support at least one of them.

  • Page 103: On To Off (Os Absent)

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.9.5 On to Off (OS absent) The SCI interrupt is masked. The firmware polls the power button status bit in the ACPI hardware registers and sets the state of the machine in the chipset to the OFF state. The mBMC monitors power state signals from the chipset and de-asserts PS_PWR_ON to the power supply.

  • Page 104: 4.10 Security

    System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 If an ACPI operating system is loaded, the following can cause the system to wake up: the PME, RTC, or Wake-On-LAN. Table 46. Supported Wake Events Wake Event Supported via ACPI (by sleep state)

  • Page 105: Operating Model

    Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.10.1 Operating Model The following table summarizes the operation of security features supported by the BIOS. Table 47. Security Features Operating Model Mode Entry Entry Criteria Behavior Exit Criteria After Exit Method/...
  • Page 106 System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 Scenario #1 Administrator Password Is Not Installed User Password Is Not Installed Login Type: N/A Set Admin Password (visible) Set User Password (visible) User Access Level [Full]** (shaded) Clear User Password (hidden) ** User Access Level option will be Full and Shaded as long as the administrator/supervisor password is not installed.

  • Page 107: Password Clear Jumper

    Platform Management The server boards support the Intel onboard platform instrumentation level of management. Integrated onto the server board is a National Semiconductor* PC87431 Mini-BMC (mBMC) that supports the functionality of the Essentials level of management. These server boards do not support the Flexible Management Connector that supports the optional Professional or Advanced Intel®...

  • Page 108: Figure 13. Block Diagram Of Platform Managment Architecture

    Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 CPU1 VRD OUTEN & System PWRGD Logic FMC_CPU1_SKTOCC_N CPU1 CPU2 VRD OUTEN Logic HECETA 7 FMC_CPU2_SKTOCC_N SUS_STAT_ GPIO48 GPIO40 RTCRST_N CPU1_PROCHOT_N P1_VID[5:0] VID_CPU0[5:0] P1_Prochot_N CPU2 GTL to translation Logic 6300ESB CPU2_PROCHOT_N P2_VID[5:0]...

  • Page 109: Standby

    Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management 5.1.1 5V Standby The power supply must provide a 5V Standby power source for the platform to provide any management functionality. 5V Standby is a low power 5V supply that is active whenever the system is plugged into AC power.

  • Page 110: Ipmi Sensor Model

    Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 5.1.3 IPMI Sensor Model An IPMI-compatible sensor model is used to unify the way that temperature, voltage, and other platform management status and control is represented and accessed. The implementation of this model is done according to command and data formats defined in the Intelligent Platform Management Interface Specification.

  • Page 111: Mini-Baseboard Management Controller

    Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management 5.1.5 Mini-Baseboard Management Controller At the heart of platform management is a management controller. To support the onboard platform instrumentation management model, the server boards incorporate the National Semiconductor* PC87431 Mini-BMC (mBMC).
  • Page 112 Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 The following are the common features supported by the mBMC. Power system System reset control System initialization Watchdog timer System event log Sensor data record (SDR) repository Field replaceable unit (FRU) inventory device...

  • Page 113: Onboard Platform Instrumentation Features And Functionality

    Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management Onboard Platform Instrumentation Features and Functionality The National Semiconductor* PC87431 management controller is an Application Specific Integrated Circuit (ASIC) with many peripheral devices embedded into it. The mBMC contains the logic needed for controlling the system, monitoring the sensors, and communicating with other systems and devices via various external interfaces.

  • Page 114: Mbmc Self-Test

    Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 5.2.1 mBMC Self-test The mBMC performs various tests as part of its initialization. If a failure is determined, the mBMC stores the error internally. A failure may be caused by a corrupt mBMC FRU, SDR, or SEL.

  • Page 115: Messaging Interfaces

    Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management 5.2.3.1 Private Management I C Buses The mBMC implements a single private management bus. The mBMC is the sole master on this bus. External agents must use the mBMC Master Write/Read I C command if they require direct communication with a device on this bus.
  • Page 116 Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 5.2.4.4 Host to mBMC Communication Interface The host communicates with the mBMC via the System Management Bus (SMBus). The interface consists of three signals: SMBus clock signal (SCLH) SMBus data signal (SDAH) Optional SMBus alert signal (SMBAH).

  • Page 117: Direct Platform Control (Ipmi Over Lan)

    UDP port 26Fh is a ‘well known port’ address that is specified to carry RMCP (Remote Management Control Protocol) formatted UDP datagrams. The onboard Intel network interface controllers contain circuitry that enables detecting and capturing RMCP packets that are received on Port 26Fh and making them available to the management controller via a ‘side-...

  • Page 118: Table 50. Lan Channel Specifications

    Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 RMCP In-band Port Traffic 26Fh NIC #1 mBMC side-band connection System Bus Figure 16. IPMI-over-LAN RMCP includes a field that indicates the class of messages that can be embedded in an RMCP message packet.

  • Page 119: Wake On Lan / Power On Lan And Magic Packet Support

    5.2.5.2 LAN Drivers and Setup The IPMI-over-LAN feature must be used with the appropriate Intel NIC Driver, and the NIC correctly configured in order for DPC LAN operation to occur transparently to the operating system and network applications. If an incorrect driver or NIC configuration is used, it is possible to get driver timeouts when the IPMI-over-LAN feature is enabled.

  • Page 120: Watchdog Timer

    Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 5.2.7 Watchdog Timer The mBMC implements an IPMI 1.5-compatible watchdog timer. See the IPMI specification for details. SMI and NMI pre-timeout actions are supported, as are hard reset, power down, and power cycle timeout actions.

  • Page 121: Sensor Data Record (Sdr) Repository

    Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management 5.2.9 Sensor Data Record (SDR) Repository The mBMC includes built-in sensor data records that provide platform management capabilities (sensor types, locations, event generation and access information). The SDR repository is accessible via all communication transports. This way, out-of-band interfaces can access the SDR repository information if the system is down.

  • Page 122: Table 51. Pef Action Priorities

    Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 The mBMC maintains an Event Filter table with 30 entries that is used to select the actions to perform. Also maintained is a fixed/read-only Alert Policy Table entry. No alert strings are supported.
  • Page 123 Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management Event Filter # Offset Mask Events Degraded Proc 1-2 FRB3 Deassert Degraded Proc 1-2 Hot Assert Degraded Proc 1-2 Hot Deassert Critical FP NMI Assert Critical FP NMI Deassert Non Critical SCSI Terminator Fail Assert...

  • Page 124: Nmi Generation

    Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 The user does not typically deal with filter contents directly. Instead, the Server Setup Utility provides a user interface that allows the user to select among a fixed set of pre-configured event filters.

  • Page 125: Smi Generation

    Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management the system crash state can use the Get NMI Source command to determine and save the cause of the NMI. 5.2.13 SMI Generation The mBMC can generate an SMI due to watchdog timer pre-timeout expiration with SMI pre- timeout interrupt specified.

  • Page 126: Table 53. Power Control Initiators

    Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 5.3.1.1 Power-up Sequence When turning on the system power in response to one of the event occurrences listed in Table 53 below, the mBMC executes the following procedure: The mBMC asserts Power On and waits for the power subsystem to assert Power Good.

  • Page 127: System Reset Control

    Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management 5.3.2 System Reset Control 5.3.2.1 Reset Signal Output The mBMC asserts the System Reset signal on the server board to perform a system reset. The mBMC asserts the System Reset signal before powering the system up. After power is stable...

  • Page 128: Front Panel Control

    The management controller firmware expects to find an LM30 temperature sensor on the front panel board. Thus, the ambient temperature-based fan speed control capability is not enabled by default for SE7320SP2 or SE7525GP2 as a server board-only product, but can be enabled via a management controller configuration change.
  • Page 129 Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management 5.3.4.2 Reset Button The reset button is a momentary contact button on the front panel. Its signal is routed through the front panel connector to the mBMC, which monitors and de-bounces it. The signal must be stable for at least 25ms before a state change is recognized.

  • Page 130: Table 55. Chassis Id Leds

    Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 The Chassis Identify Push-button works using a “push-on/push-off” operation. Each press of the push-button toggles the LED signal state between on and off. If the pushbutton is used to turn the LED on, it will stay on indefinitely, until either the button is pressed again or a Chassis Identify or Chassis Identify LED command causes the LED to turn off.

  • Page 131: Secure Mode Operation

    Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management on-Critical Condition Temperature, voltage, or fan non-critical threshold crossing Chassis intrusion Satellite controller sends a non-critical state, via the Set Fault Indication command, to the mBMC Set Fault Indication command from system BIOS. The BIOS may use the Set Fault Indication command to indicate additional, non-critical status such as system memory or CPU configuration changes.

  • Page 132: Fru Information

    Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 If it is enabled, Secure Mode can be controlled via the Secure Mode KB signal from the keyboard controller. When Secure Mode is active, pressing a protected front panel switch generates a Secure Mode Violation event. Specifically, this generates an assertion of the Secure Mode Violation Attempt offset of the mBMC’s Platform Security Violation Attempt...

  • Page 133: Sensors

    Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management Sensors 5.4.1 Sensor Type Codes The following tables list the sensor identification numbers and information regarding the sensor type, name, supported thresholds, assertion and deassertion information, and a brief description of the sensor purpose. Refer to the Intelligent Platform Management Interface Specification, Version 1.5, for sensor and event/reading-type table information.

  • Page 134: Table 57. Mbmc Built-In Sensors

    Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 Table 57. mBMC Built-in Sensors Event / Readable Event Offset Assert / Sensor Name Sensor # Sensor Type Reading Value / EventData Triggers Deassert Type Offsets Physical Security Physical Sensor LAN Leash...

  • Page 135: Table 59. External Platform Sensors

    Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management Event / Readable Sensor Event Offset Assert / Sensor Name Sensor Type Reading Value / Event Data Triggers Deassert Type Offsets Timer Expired Hard Reset Sensor Watchdog2 Watchdog Specific Power Down –...
  • Page 136 Platform Management Intel® Server Boards SE7320SP2 and SE7525GP2 Event / Event Sensor Assert / Readable Event Sensor Name Reading Offset Record Type Deassert Value/Offsets Data Action Type Triggers Type Fault Voltage Threshold BB -12V [u,l][ nr, c,nc] As & De...
  • Page 137 Intel® Server Boards SE7320SP2 and SE7525GP2 Platform Management Event / Event Sensor Assert / Readable Event Sensor Name Reading Offset Record Type Deassert Value/Offsets Data Action Type Triggers Type Fault Temp Threshold Trig Proc2 Throttle [u,l][ nr, c,nc] As & De...

  • Page 138: Error Reporting And Handling

    The error codes are defined by Intel and whenever possible are backward compatible with error codes used on earlier platforms.
  • Page 139 Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling PERR# and SERR# through NMI. Disabling NMI for PERR# and/or SERR# also disables logging of the corresponding event. In the case of PERR#, the PCI bus master has the option to retry the offending transaction, or to report it using SERR#.

  • Page 140: Single-Bit Ecc Error Throttling Prevention

    Error Reporting and Handling Intel® Server Boards SE7320SP2 and SE7525GP2 6.1.2.6 Boot Event The BIOS downloads the system date and time to the mBMC during POST and logs a boot event. This record does not indicate an error, and software that parses the event log should treat it as such.

  • Page 141: Error Messages And Error Codes

    The error codes are defined by Intel and whenever possible are backward compatible with error codes used on earlier platforms.
  • Page 142 Error Reporting and Handling Intel® Server Boards SE7320SP2 and SE7525GP2 Error Code Error Message Response 0010 Floppy Controller Failure Pause 0012 CMOS time not set Pause 0014 PS2 Mouse not found Not an error 0040 Refresh timer test failed Halt...
  • Page 143 Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling Error Code Error Message Response 5120 CMOS Cleared By Jumper Pause 5121 Password cleared by jumper Pause 5122 CMOS Cleared By BMC Request Pause 8104 Warning! Port 60h/64h emulation is not supported by this USB Host Controller !!!

  • Page 144: Boot Block Error Beep Codes

    Error Reporting and Handling Intel® Server Boards SE7320SP2 and SE7525GP2 6.2.2 Boot Block Error Beep Codes Table 61. Boot Block Error Beep Codes Number of Beeps Description Insert diskette in floppy drive A: ‘AMIBOOT.ROM’ file not found in root directory of diskette in A:...

  • Page 145: Post Error Pause" Option

    Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling Number of Beeps Troubleshooting Action 1, 2 or 3 Reseat the memory, or replace with known good modules. 4-7, 9-11 Fatal error indicating a serious problem with the system. Consult your system manufacturer.

  • Page 146: Table 64. Post Progress Code Led Example

    Error Reporting and Handling Intel® Server Boards SE7320SP2 and SE7525GP2 Since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble, the two are concatenated to be ACh. Table 64. POST Progress Code LED Example...

  • Page 147: Post Code Checkpoints

    Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling 6.3.3 POST Code Checkpoints Table 65. POST Code Checkpoints Diagnostic LED Decoder Description Checkpoint G=Green, R=Red, A=Amber Disable NMI, parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Run-time data area. Initialize BIOS modules on POST entry and GPNV area.
  • Page 148 Error Reporting and Handling Intel® Server Boards SE7320SP2 and SE7525GP2 Diagnostic LED Decoder Description Checkpoint G=Green, R=Red, A=Amber Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs. Initializes all the output devices.

  • Page 149: Bootblock Initialization Code Checkpoints

    Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling Diagnostic LED Decoder Description Checkpoint G=Green, R=Red, A=Amber Displays the system configuration screen if enabled. Initialize the CPU’s before boot, which includes the programming of the MTRR’s. Prepare CPU for operating system boot including final MTRR values.

  • Page 150: Bootblock Recovery Code Checkpoint

    Error Reporting and Handling Intel® Server Boards SE7320SP2 and SE7525GP2 Diagnostic LED Decoder Description Checkpoint G=Green, R=Red, A=Amber The Runtime module is uncompressed into memory. CPUID information is stored in memory. Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory.

  • Page 151: Dim Code Checkpoints

    Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h. 6.3.6 DIM Code Checkpoints The Device Initialization Manager (DIM) module gets control at various times during BIOS POST to initialize different buses.

  • Page 152: Memory Error Codes

    Error Reporting and Handling Intel® Server Boards SE7320SP2 and SE7525GP2 6.3.8 Memory Error Codes Table 70. Memory Error Codes Tpoint Description 001h MEM_ERR_CHANNEL_B_OFF (DIMM mismatch forced Channel B disabled) 002h MEM_ERR_CK_PAIR_OFF (Slow DIMM(s) forced clock pair disabled) 0E1h MEM_ERR_NO_DEVICE (No memory installed)

  • Page 153: Connector Definitions And Pin-Outs

    Intel® Server Boards SE7320SP2 and SE7525GP2 Connector Definitions and Pin-outs Connector Definitions and Pin-outs Main Power Connector The main power supply connection is obtained using the 24-pin connector. The following table defines the pin-outs of the connector. Table 71. Power Connector Pin-out (J12)

  • Page 154: Memory Module Connector

    Connector Definitions and Pin-outs Intel® Server Boards SE7320SP2 and SE7525GP2 Table 73. Auxiliary CPU Power Connector Pin-out (J22) Signal 18 AWG color Signal 18 AWG Color Black +12V1 White Black 12V1 RS Yellow (24AWG) Black +12V1 White Black +12V2 Brown...

  • Page 155: Processor Socket

    Intel® Server Boards SE7320SP2 and SE7525GP2 Connector Definitions and Pin-outs Front Front Front Back Back Back DQS2 DQ33 DQS7 DQ21 DQ37 DQ62 DQS4 DQ58 DQ63 DQ34 DQ59 VDDQ DQ18 DQ38 DQ22 DQ39 VDDQ DQ35 DQ19 DQ40 DQ23 DQ44 VDDSPD Note: * These pins are not used in this module.
  • Page 156 Connector Definitions and Pin-outs Intel® Server Boards SE7320SP2 and SE7525GP2 Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name HIT# AB27 Reserved AB28 AB29 AB30 AB31 FERR#/PBE# Reserved VIDPWRGD...
  • Page 157 Intel® Server Boards SE7320SP2 and SE7525GP2 Connector Definitions and Pin-outs Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name D62# D57# RSP# DSTBP3# D46# DSTBN3# A35# AD10 D45# A34#...

  • Page 158: I 2 C Headers

    These are “Reserved ” pins on the Intel Xeon processor. In systems utilizing the Intel Xeon processor, the system designer must terminate these signals to the processor VTT. Server boards treating AA3 and AB3 as Reserved will operate correctly with a bus clock of 200 MHz.

  • Page 159: Pci Slot Connector

    Intel® Server Boards SE7320SP2 and SE7525GP2 Connector Definitions and Pin-outs Table 78. Remote Management Card Header Pin-out (J33) Signal Name Description MBMC_SMB_PHL_DAT Data Line GROUND MBMC_SMB_PHL_CLK Clock Line P5V_STBY POWER PCI Slot Connector There are three PCI buses implemented on the server board. PCI segment A supports 5V 32- bit/33 MHz PCI, segment B supports 3.3V 64-bit/66 MHz PCI-X, and segment C supports 3.3V...

  • Page 160: Table 80. P64-B 3.3V 64-Bit/66-Mhz Pci-X Slot Pin-Out (J8, J9)

    Connector Definitions and Pin-outs Intel® Server Boards SE7320SP2 and SE7525GP2 Side B Side A Side B Side A AD[27] AD[26] +3.3V AD[06] AD[25] Ground AD[05] AD[04] +3.3V AD[24] AD[03] Ground C/BE[3]# IDSEL Ground AD[02] AD[23] +3.3V AD[01] AD[00] Ground AD[22]...

  • Page 161: Table 81. Pci Express* Slot Pin-Out (J13 For X4, J14 For X16)

    Intel® Server Boards SE7320SP2 and SE7525GP2 Connector Definitions and Pin-outs Side B Side A Side B Side A AD[19] Ground Ground AD[52] +3.3V AD[18] AD[51] AD[50] AD[17] AD[16] AD[49] Ground C/BE[2]# +3.3V +3.3V (I/O) AD[48] Ground FRAME# AD[47] AD[46] IRDY#...
  • Page 162 Connector Definitions and Pin-outs Intel® Server Boards SE7320SP2 and SE7525GP2 Side B Side A Side B Side A HSON10 End of the x1 Connector HSOP1 RSVD HSIP10 HSON1 HSIN10 HSIP1 HSOP11 HSIN1 HSON11 HSOP2 HSIP11 HSON2 HSIN11 HSIP2 HSOP12 HSIN2...

  • Page 163: Front Panel Connector

    Intel® Server Boards SE7320SP2 and SE7525GP2 Connector Definitions and Pin-outs Front Panel Connector A standard SSI 34-pin header is provided to support a system front panel. The header contains reset, NMI, power control buttons, and LED indicators. The following table details the pin-out of this header.

  • Page 164: Vga Connector

    Connector Definitions and Pin-outs Intel® Server Boards SE7320SP2 and SE7525GP2 VGA Connector The following table details the pin-out of the VGA connector. This connector is combined with COM1 connector. Table 83. VGA Connector Pin-out (J4) Signal Name Signal Name Fused VCC (+5V) (NO SUPPORT)

  • Page 165: Ide Connector

    Intel® Server Boards SE7320SP2 and SE7525GP2 Connector Definitions and Pin-outs IDE Connector The board provides two 40-pin ATA-100 IDE connectors Table 85. ATA 40-pin Connector Pin-out (J41, J43) Signal Name Signal Name RESET# IDE_DD7 IDE_DD8 IDE_DD6 IDE_DD9 IDE_DD5 IDE_DD10 IDE_DD4...

  • Page 166: 7.11 Usb Connector

    Connector Definitions and Pin-outs Intel® Server Boards SE7320SP2 and SE7525GP2 7.11 USB Connector The following table provides the pin-out for the dual external USB connectors. Table 87. USB Connectors Pin-out (J3) Signal Name Fused VCC (+5V /w over current monitor of both port 3)

  • Page 167: 7.12 Floppy Connector

    Intel® Server Boards SE7320SP2 and SE7525GP2 Connector Definitions and Pin-outs 7.12 Floppy Connector The board provides a standard 34-pin interface to the floppy drive controller. The following tables detail the pin-out of the 34-pin floppy connector. Table 89. Legacy 34-pin Floppy Connector Pin-out (J47)

  • Page 168: 7.13 Serial Port Connector

    Intel® Server Boards SE7320SP2 and SE7525GP2 7.13 Serial Port Connector Two serial ports are provided on the SE7320SP2 and Server Board SE7525GP2. A standard, external DB9 serial connector is located on the back edge of the server board to supply a Serial A interface. And this connector is combined with VGA connector (J4) A Serial B port is provided through a 9-pin header (J15) on the server board.

  • Page 169: 7.14 Keyboard And Mouse Connector

    Intel® Server Boards SE7320SP2 and SE7525GP2 Connector Definitions and Pin-outs 7.14 Keyboard and Mouse Connector Two PS/2 ports are provided for use by a keyboard and a mouse. The following table details the pin-out of the PS/2 connectors. Table 92. Keyboard and Mouse PS/2 Connectors Pin-out (J2)

  • Page 170: Intrusion Cable Connector

    Connector Definitions and Pin-outs Intel® Server Boards SE7320SP2 and SE7525GP2 Table 94. Six-pin Fan headers Pin-out (J44, J46) Signal Name Type Description Ground Power GROUND is the power supply ground Fan Power Power Fan Power Fan Tach FAN_TACH signal is connected to the Super I/O to monitor the FAN speed.

  • Page 171: 7.16 Configuration Jumpers

    Intel® Server Boards SE7320SP2 and SE7525GP2 Connector Definitions and Pin-outs 7.16 Configuration Jumpers This section describes the configuration jumpers on the server boards. 7.16.1 System Recovery and Update Jumpers The server boards provide an 11-pin single inline header (J17), located on the edge of the server board next to PCI Slot 1, this header provides a total of three 3-pin jumper blocks that are used to configure several system recovery and update options.

  • Page 172: Rolling Bios Bank Selection Jumper

    Connector Definitions and Pin-outs Intel® Server Boards SE7320SP2 and SE7525GP2 7.16.2 Rolling BIOS Bank Selection Jumper An additional 3-pin jumper header (J26) is provided to support the Rolling BIOS functionality. This jumper is located near the processor 2 VRD heatsink and the SATA connectors on the board.

  • Page 173: General Specifications

    VDD means supply voltage for the device Note: Intel Corporation server boards contain a number of high-density VLSI and power delivery components which need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components.

  • Page 174: Processor Power Support

    General Specifications Intel® Server Boards SE7320SP2 and SE7525GP2 Processor Power Support ® The server boards are designed to support the Thermal Design Point (TDP) guideline for Intel ® Xeon processors. In addition, the Flexible Motherboard Guidelines (FMB) have been followed to help determine the suggested thermal and current design values for anticipating future processor needs.

  • Page 175: Table 103. Voltage Timing Parameters

    Intel® Server Boards SE7320SP2 and SE7525GP2 General Specifications Figure 21 shows the output voltage timing parameters. Vout Vout vout_off vout rise vout_on Figure 21. Output Voltage Timing The following tables show the timing requirements for a single power supply being turned on and off via the AC input, with PSON held low and the PSON signal, with the AC input applied.

  • Page 176: Table 104. Turn On / Off Timing

    General Specifications Intel® Server Boards SE7320SP2 and SE7525GP2 Table 104. Turn On / Off Timing Item Description Units Tsb_on_delay Delay from AC being applied to 5VSB being within regulation. 1500 msec T ac_on_delay Delay from AC being applied to all output voltages being within...
  • Page 177 Intel® Server Boards SE7320SP2 and SE7525GP2 General Specifications AC Input vout_holdup Vout pwok_low AC_on_delay pwok_off sb_on_delay pwok_on pwok_off sb_on_delay pwok_on PWOK pson_pwok pwok_holdup 5VSB sb_vout pson_on_delay PSON AC turn on/off cycle PSON turn on/off cycle Figure 22. Turn On / Off Timing...

  • Page 178: Voltage Recovery Timing Specifications

    General Specifications Intel® Server Boards SE7320SP2 and SE7525GP2 8.4.2 Voltage Recovery Timing Specifications The power supply must conform to the following specifications for voltage recovery timing under load changes: Voltage shall remain within +/- 5% of the nominal set voltage on the +5 V, +12 V, 3.3 V, - 5 V and -12 V output, during instantaneous changes in load shown in the following table.

  • Page 179: Product Regulatory Compliance

    Product EMC Compliance The server boards have been tested and verified to comply with the following electromagnetic compatibility (EMC) regulations when installed in a compatible Intel host system. For information on compatible host system(s), contact your local Intel representative. FCC/ICES-003 Verification to Class A Emissions (USA/Canada)

  • Page 180: Mandatory/Standard: Certifications, Registration, Declarations

    Product Regulatory Compliance Intel® Server Boards SE7320SP2 and SE7525GP2 9.1.2 Mandatory/Standard: Certifications, Registration, Declarations UL Recognition (US/Canada) CE Declaration of Conformity (CENELEC Europe) FCC/ICES-003 Class A Verification (USA/Canada) VCCI Certification (Japan) – Verification Only C-Tick Declaration of Conformity (Australia) MOC Declaration of Conformity (New Zealand)

  • Page 181: Ministry Of Economic Development (New Zealand) Declaration Of Conformity

    Intel® Server Boards SE7320SP2 and SE7525GP2 Product Regulatory Compliance 9.2.3 Ministry of Economic Development (New Zealand) Declaration of Conformity This product has been tested to AS/NZS 3548, and complies with New Zealand’s Ministry of Economic Development emission requirements. 9.2.4 BSMI (Taiwan) The BSMI Certification number R33025 is silk screened on the component side of the server board;...

  • Page 183: Appendix A: Integration And Usage Tips

    Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips ® This section provides a bullet list of useful information that is unique to the Intel Server Boards SE7320SP2 and SE7525GP2 and should be kept in mind while assembling and configuring a system based on either of these boards.

  • Page 184: Glossary

    Glossary Intel® Server Boards SE7320SP2 and SE7525GP2 Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.

This manual is also suitable for:

Se7320sp2

Table of Contents