Intel SE7520AF2 Technical Product Specification

Intel SE7520AF2 Technical Product Specification

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Intel® Server Board
SE7520AF2
Technical Product Specification
Intel order number C77866-003
Revision 1.2
March, 2005
Enterprise Platforms and Services Marketing

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Summary of Contents for Intel SE7520AF2

  • Page 1 Intel® Server Board SE7520AF2 Technical Product Specification Intel order number C77866-003 Revision 1.2 March, 2005 Enterprise Platforms and Services Marketing...
  • Page 2 Added integrated Intel® RAID Controller SROMBU42E Chapter 08/2004 First public release Q1’2005 Update (rolled Spec Update documentation changes and updated 01/2005 BIOS Setup screen changes) 03/2005 Updated mBMC and Intel Management Module platform sensors tables Revision 1.2 Intel order number C77866-003...
  • Page 3 Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
  • Page 4 Table of Contents Intel® Server Board SE7520AF2 TPS < This page intentionally left blank. > Revision 1.2 Intel order number C77866-003...
  • Page 5: Table Of Contents

    1. Introduction ........................21 Chapter Outline...................... 21 Server Board Use Disclaimer ................22 2. Server Board Overview ...................... 23 Intel® Server Board SE7520AF2 SKU Options ............. 23 Intel® Server Board SE7520AF2 Feature Set ............23 Server Board Layout....................25 2.3.1 Component Placement ..................
  • Page 6 Hardware Initialization ................... 80 Clock Generation and Distribution ................. 81 4. Integrated Intel® RAID Controller SROMBU42E.............. 83 Overview........................ 83 Primary Integrated Intel RAID Controller SROMBU42E Features ......83 4.2.1 Configuration on Disk .................... 85 4.2.2 Array Performance Features ................. 85 4.2.3...
  • Page 7 Intel® Server Board SE7520AF2 TPS Table of Contents 4.4.6 Levels of Drive Hierarchy within the Intel® Integrated RAID Firmware ....92 Intel® RAID Controller Drivers................93 Intel® RAID Web Console ..................93 Intel® RAID BIOS Console Configuration Utility............ 94 4.7.1 Quick Configuration Steps ..................
  • Page 8 Table of Contents Intel® Server Board SE7520AF2 TPS PCI Initialization ....................112 5.5.1 Scan Order ......................112 5.5.2 Resource Assignment..................112 5.5.3 Automatic IRQ Assignment.................. 112 5.5.4 Option ROMs ....................... 112 5.5.5 PCI APIs ......................113 5.5.6 Split Option ROM....................113 5.5.7...
  • Page 9 Intel® Server Board SE7520AF2 TPS Table of Contents 5.14.4 Update OEM Logo ....................141 5.15 OEM Binary ......................142 5.15.1 Scan Point Definitions..................144 5.15.2 Format of the OEM Binary Structure..............145 5.16 Quiet Boot / OEM Splash Screen ................ 145 5.17...
  • Page 10 Table of Contents Intel® Server Board SE7520AF2 TPS 6.3.2 System Reset Control ..................171 6.3.3 Temperature-based Fan Speed Control .............. 172 6.3.4 Front Panel Control....................172 6.3.5 FRU Information ....................176 Sensors........................ 176 6.4.1 Sensor Type Codes ..................... 176 7. Error Reporting and Handling ..................189 Fault Resilient Booting (FRB) ................
  • Page 11 Intel® Server Board SE7520AF2 TPS Table of Contents 8.6.3 IPMB Header ....................... 229 8.6.4 OEM RMC Header....................229 8.6.5 HSBP Header ...................... 229 PCI Slot Connector ....................229 Front Panel Connectors..................233 VGA Connector....................234 8.10 SCSI Connector....................234 8.11 NIC Connectors ....................
  • Page 12 Table of Contents Intel® Server Board SE7520AF2 TPS 11.2.7 BSMI (Taiwan) ..................... 251 11.3 Replacing the Back-Up Battery................251 Integration and Usage Tips......................I Glossary............................II Reference Specifications and Documents ................V Revision 1.2 Intel order number C77866-003...
  • Page 13 Figure 11. Interrupt Routing Diagram ..................59 Figure 12. Intel® Portable Cache Module.................. 63 Figure 13. Video Controller PCI Bus Interface................67 Figure 14. Intel® Xeon Processor Memory Address Space ............71 Figure 15. DOS Compatibility Region ..................72 Figure 16. Extended Memory Map..................... 74 Figure 17.
  • Page 14 Figure 39. Power Supply Control Signals ................. 170 Figure 40. Location of Diagnostic LEDs on Baseboard ............200 Figure 41. SE7520AF2 Configuration Jumpers (J1D1) ............241 Figure 42. SE7520AF2 BIOS Bank Jumper (J2J6)..............242 Figure 43. Output Voltage Timing ..................... 245 Figure 44.
  • Page 15 Table 17. IOP332 P64-B Arbitration Connections ..............55 Table 18. PCI Interrupt Routing/Sharing..................56 Table 19. Interrupt Definitions....................57 Table 20. Intel® Server Board SE7520AF2 Video Modes ............65 Table 21. Video Memory Interface..................... 66 Table 22. NIC2 Status LED......................68 Table 23.
  • Page 16 List of Tables Intel® Server Board SE7520AF2 TPS Table 33. RAID Level Migration Matrix ..................87 Table 34. Adapter Properties Menu Options................96 Table 35. BIOS Features ......................105 Table 36. DIMM Population ..................... 110 Table 37. Module Capacity ...................... 110 Table 38.
  • Page 17 Table 77. Chassis ID LEDs....................... 174 Table 78. Fault/Status LED....................... 174 Table 79. mBMC Built-in Sensors..................... 177 Table 80. Intel® Server Board SE7520AF2 Sensors for OB Platform Instrumentation Management ........................178 Table 81. Platform Sensors for the Intel® Management Module ..........180 Table 82.
  • Page 18 List of Tables Intel® Server Board SE7520AF2 TPS Table 102. USB BIOS Error Messages..................211 Table 103. SMBIOS BIOS Error Messages ................212 Table 104. POST Error Messages and Handling..............212 Table 105. Management Module POST Error Codes and Messages........214 Table 106.
  • Page 19 Table 140. Configuration Jumper Options ................241 Table 141. BIOS Bank Jumper Option..................242 Table 142. Absolute Maximum Ratings ..................243 Table 143. Intel® Xeon™ processor DP TDP Guidelines............243 Table 144. SE7520AF2 Power Budget ..................244 Table 145. SE7520AF2 Power Supply Voltage Specification........... 244 Table 146.
  • Page 20 List of Tables Intel® Server Board SE7520AF2 TPS < This page intentionally left blank. > Revision 1.2 Intel order number C77866-003...
  • Page 21: Introduction

    Intel® Server Board SE7520AF2 Baseboard Management Controller (BMC) EPS Server Management EAS Hot Swap Controller Interface EPS These documents are not made publicly available and must be ordered by your local Intel representative. Chapter Outline This document is divided into the following chapters Chapter 1 –...
  • Page 22: Server Board Use Disclaimer

    Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated platform will meet the intended thermal requirements of these components. It is the...
  • Page 23: Server Board Overview

    Intel® Server Board SE7520AF2 SKU Options In this document, the product name Intel® Server Board SE7520AF2 is used to describe the family of boards that will be made available under a common marketing name. The core features for each board are common; however each board will have the following distinctions: Board SKU 1 –...
  • Page 24 SSI-EEB3.5 compliant board form factor (12 x 13 inches) SSI-compliant connectors for SSI interface supporting the 34-pin front panel, floppy, ATA-100 and power connectors Custom LCD connector enabling support for the Intel® Local Control Panel (optional accessory) Intel® Light Guided Diagnostics on critical FRU devices (processors, memory, power) Port-80 Diagnostic LEDs to display Port-80 HEX codes <The rest of this page intentionally left blank>...
  • Page 25: Server Board Layout

    Intel® Server Board SE7520AF2 TPS Server Board Overview Server Board Layout 2.3.1 Component Placement The following figure shows the board layout of the server board. HP PCI REAR SYS FAN 6 ID LED STATUS LED POST LEDS ATTENTION LEDS SYS FAN 5...
  • Page 26: Mechanical Drawing

    Server Board Overview Intel® Server Board SE7520AF2 TPS 2.3.2 Mechanical Drawing The following mechanical drawing shows the physical dimensions of the server board. Figure 2. Board Dimensions Revision 1.2 Intel order number C77866-003...
  • Page 27: Atx I/O Layout

    Intel® Server Board SE7520AF2 TPS Server Board Overview 2.3.3 ATX I/O Layout The following figure shows the ATX rear I/O layout of the Server Board SE7520AF2 Figure 3. ATX Rear IO Connectors Revision 1.2 Intel order number C77866-003...
  • Page 28 Server Board Overview Intel® Server Board SE7520AF2 TPS < This page intentionally left blank. > Revision 1.2 Intel order number C77866-003...
  • Page 29: Functional Architecture

    Intel® Server Board SE7520AF2 TPS Functional Architecture Functional Architecture This chapter provides a high-level description of the functionality associated with the architectural blocks that comprise the Intel® Server Board SE7520AF2. Figure 4. Server Board Block Diagram Revision 1.2 Intel order number C77866-003...
  • Page 30: Intel® E7520 Chipset

    Intel® 80332 I/O Processor with Intel® XScale Technology (IOP332) The following sub-sections provide an overview of the primary functions and supported features of each chipset component used on the Intel® Server Board SE7520AF2. Later sections in this chapter provide more detail on how each sub-system is implemented.
  • Page 31 The Intel® E7520 MCH supports either single or dual processor configurations using the Intel® Xeon™ processor with 1 MB L2 cache or the Intel® Xeon™ processor with 2 MB L2 cache. The MCH supports a base system bus frequency of 200 MHz. The address and request interface is double pumped to 400 MHz while the 64-bit data interface (+ parity) is quad pumped to 800 MHz.
  • Page 32 Functional Architecture Intel® Server Board SE7520AF2 TPS 3.1.1.3.1 PCI Express* Training To establish a connection between PCI Express* endpoints, the endpoints participate in a sequence of steps known as training. This sequence establishes the operational width of the link and adjusts skews of the various lanes within a link so that the data sample points can correctly take a data sample from the link.
  • Page 33: Table 1. Pci Express* Hot-Plug Led Function Table

    3.1.1.3.6 PCI Express* Hot-Plug Support Hot-plug support is available on the PCI Express* expansion slots (Slot 3, Slot 4) on the Intel® Server Board SE7520AF2 (SE7520HPAF2 SKU only). The PCI Express* hot-plug controller follows the requirements and recommendations from PCI Express* Base Specification, Rev 1.0.
  • Page 34: Pci-X Hub (Pxh)

    Intel® Server Board SE7520AF2 TPS 3.1.1.4 Hub Link 1.5 Interface The MCH interfaces with the Intel® 82801ER I/O Controller Hub 5-R (ICH5-R) via a dedicated Hublink Interface supporting a peak bandwidth of 266MB/s using a x4 base clock of 66 MHz. 3.1.2...
  • Page 35: Iop332 I/O Processor

    The IOP332 I/O processor is fully compliant with the PCI Local Bus Specification, Rev 2.3 and the PCI Express* Specification, Rev 1.0. The IOP332 I/O processor on the Intel® Server Board SE7520AF2 is enabled via a x4 PCI Express* port from the MCH. This I/O processor enables RAID On Mother Board (ROMB) support with the optional Intel®...
  • Page 36 5-V tolerant, except PME#. The ICH5 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH5 requests. On the Intel® Server Board SE7520AF2 this PCI interface is used to support one on-board PCI device: ATI* Rage XL video controller.
  • Page 37 USB full-speed and low-speed signaling. The Intel® Server Board SE7520AF2 makes use of five of the six USB 2.0 ports from the ICH5- R: three available in the rear I/O area and two available via a DH10 header on the board that Revision 1.2...
  • Page 38: Table 3. Ich5-R Gpio Assignment

    Functional Architecture Intel® Server Board SE7520AF2 TPS can be routed to the front of the server. All five ports are high-speed, full-speed, and low-speed capable. 3.1.4.8 Real-time Clock (RTC) The ICH5-R contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery backed RAM.
  • Page 39: Processor Sub-System

    The Intel® Server Board SE7520AF2 supports either one or two Intel® Xeon™ processors with 1MB L2 cache or Intel® Xeon™ processors with 2MB L2 cache with frequencies starting at 2.8 GHz using 90 nanometer technology and utilizing an 800MHz front side bus. Previous generations of the Intel Xeon processor are not supported.
  • Page 40: Processor Vrd

    FC-mPGA4 90 nM 3.8 GHz 1024KB The Intel® Server Board SE7520AF2 is designed to provide up to 120A per processors. Processors with higher current requirements are not supported. 3.2.1 Processor VRD The baseboard has two VRDs (Voltage Regulator Down) providing the appropriate voltages to the installed processors.
  • Page 41: Gtl2006

    3.2.5 Common Enabling Kit (CEK) Design Support The baseboard has been designed to comply with the Intel® Common Enabling Kit (CEK) processor mounting and thermal solution. The baseboard ships from Intel’s factory with a CEK spring snapped onto the underside of the board, beneath each processor socket. The CEK spring is removable to allow the use of non-Intel heat sink retention solutions.
  • Page 42: Supported Memory

    3.3.1 Supported Memory The Intel® Server Board SE7520AF2 supports four single-ranked registered DDR2-400 DIMMs per channel, which provides a total of eight DIMMs. The maximum memory capacity supported is 16 GB using eight modules of 1 Gbit DRAM technology devices.
  • Page 43: Figure 6. Dimm Socket Configuration

    Intel® Server Board SE7520AF2 TPS Functional Architecture Bank 4 Bank 3 Bank 2 Bank 1 Figure 6. DIMM Socket Configuration DIMM and memory configurations must adhere to the following: DDR2-400 MHz registered ECC DIMM modules DIMM organization: x72 ECC Pin count: 240 pins...
  • Page 44: Single Channel Operation

    DIMM type and/or vendors. 3.3.4 C Bus To boot the system, the system BIOS on the Intel® Server Board SE7520AF2 uses a dedicated C bus to retrieve DIMM information needed to program the MCH memory registers. The following table provides the I C addresses for each DIMM slot.
  • Page 45 3.3.6.2 Integrated Memory Scrub Engine The Intel® E7520 MCH includes an integrated engine to walk the populated memory space proactively seeking out soft errors in the memory subsystem. In the case of a single bit correctable error, this hardware detects, logs, and corrects the data except when an incoming write to the same memory address is detected.
  • Page 46 3.3.6.3 Retry on Uncorrectable Error The Intel® E7520 MCH includes specialized hardware to resubmit a memory read request upon detection of an uncorrectable error. When a demand fetch (as opposed to a scrub) of memory encounters an uncorrectable error as determined by the enabled ECC algorithm, the memory control hardware causes a (single) full resubmission of the entire cache line request from memory to verify the existence of corrupt data.
  • Page 47 Mirroring is supported on dual-channel DIMM populations symmetric both across channels and within each channel. As a result, the Intel® Server Board SE7520AF2 provides three supported configurations for memory mirroring: A four-DIMM population uses two identical devices per channel.
  • Page 48: Figure 7. Four Dimm Memory Mirror Configuration

    Functional Architecture Intel® Server Board SE7520AF2 TPS Empty Empty Mirror Primary Figure 7. Four DIMM Memory Mirror Configuration A six-DIMM population uses identical devices within DIMM Bank 1, and between DIMM Banks 2 and 3. Referring to Figure 8, DIMMs labeled 3A, 3B, 2A, and 2B must be single- rank and identical;...
  • Page 49: Figure 8. Six Dimm Memory Mirror Configuration

    Intel® Server Board SE7520AF2 TPS Functional Architecture Empty Mirror Primary Primary /Mirror Figure 8. Six DIMM Memory Mirror Configuration An eight-DIMM population uses identical devices in DIMM Banks 1 and 2, and in DIMM Banks 3 and 4. Referring to Figure 9, DIMMs labeled 1A, 1B, 2A, and 2B must be identical and those labeled 3A, 3B, 4A, and 4B must be identical.
  • Page 50: Figure 9. Eight Dimm Memory Mirror Configuration

    Functional Architecture Intel® Server Board SE7520AF2 TPS Figure 9. Eight DIMM Memory Mirror Configuration The symmetry requirements are a result of the hardware mechanism for maintaining two copies of all main memory data while ensuring that each channel has a full copy of all data in preparation for fail-down to single-channel operation.
  • Page 51: I/O Sub-System

    PCI-X Slot 1 The ICH5-R provides the interface for the onboard video controller, Super IO chip, and Management Sub-system This section describes the function of each I/O interface and how they operate on the Intel® Server Board SE7520AF2. 3.4.1 PCI Subsystem The primary I/O interface for the Intel®...
  • Page 52: Table 8. Ich5-R P32-A Configuration Ids

    Functional Architecture Intel® Server Board SE7520AF2 TPS ICH5-R P32-A 32-bits 33 MHz ATI* Rage XL PXH P64-A 3.3 V 64-bits 133 MHz PCI-X Slot 5 (PCI-X 64/133) Slot 6 (PCI-X 64/100) PXH P64-B 3.3 V 64-bits 100 MHz PCI-X Intel® 82546GB Dual Gb NIC...
  • Page 53: Table 10. Pxh P64-A Configuration Ids

    Standard PCI-X 1.0 compatible riser card 1U/1-slot PCI-X riser card 2U/2-slot PCI-X riser card Note: Intel does not provide a PCI riser card for this server platform. However, in this document, Intel has provided information to assist developers with their PCI riser design. 3.4.1.2.2...
  • Page 54: Table 12. Pxh P64-A Arbitration Connections

    3.4.1.2.4 PXH P64-B Arbitration The PXH P64-B bus segment supports the on-board Intel® 82546GB 10/100/1000 Dual Gigabit Ethernet controller and the PCI expansion Slot 6 (PCI-X 64/100), or Slot 6 and Slot 7 in the event of a two-slot riser. All PCI masters must arbitrate for PCI access, using resources supplied by the PXH.
  • Page 55: Interrupt Routing

    MCH PCI Express* implementation, refer to Section 3.1.1.3. 3.4.2 Interrupt Routing The Intel® Server Board SE7520AF2 interrupt architecture accommodates both PC-compatible PIC mode and APIC mode interrupts through use of the integrated I/O APICs in the ICH5-R. Revision 1.2...
  • Page 56: Table 18. Pci Interrupt Routing/Sharing

    Intel I/O APIC devices to manage and broadcast interrupts to local APICs in each processor. The Intel I/O APICs monitor each interrupt on each PCI device including PCI slots in addition to the ISA compatibility interrupts IRQ(0-15). When an interrupt occurs, a message corresponding to the interrupt is sent across a three-wire serial interface to the local APICs.
  • Page 57: Table 19. Interrupt Definitions

    Intel® Server Board SE7520AF2 TPS Functional Architecture 3.4.2.3 Legacy Interrupt Sources The table below recommends the logical interrupt mapping of interrupt sources on the Intel® Server Board SE7520AF2. The actual interrupt map is defined using configuration registers in the ICH5-R. Table 19. Interrupt Definitions...
  • Page 58: Figure 10. Interrupt Routing Diagram (Ich5-R Internal)

    Functional Architecture Intel® Server Board SE7520AF2 TPS ICH5-R IOAPIC 0 HL 1.5 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 ICH5-R IRQ7 IRQ8 ICH5-R 8259PIC IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ0 IRQ1 PCI-E INTERFACE IRQ2 IRQ3...
  • Page 59: Figure 11. Interrupt Routing Diagram

    Intel® Server Board SE7520AF2 TPS Functional Architecture Super I/O Timer Keyboard Cascade Serial Port2/ISA SERIRQ SERIRQ Serial Port1/ISA Floppy/ISA SCI/ISA Mouse/ISA Coprocessor Error P IDE/ISA Not Used PIRQA# USB 1.1 #1 and #4 PIRQB# Video PIRQC# USB 1.1 #3, Native IDE and S-ATA PIRQD# USB 1.1 #2...
  • Page 60: Scsi Support

    3.4.3 SCSI Support The SCSI sub-system on the Intel® Server Board SE7520AF2 is enabled via the LSI Logic* 53C1030 Dual Channel Ultra 320 SCSI controller, two internal 80-pin connector (SCSI Channel A and Channel B), and on-board termination for both SCSI channels.
  • Page 61 Uses the Fusion-MPT (Message Passing Technology) drivers to provide support for all Intel® Server Board SE7520AF2 supported operating systems. Refer to the Intel® Server Board SE7520AF2 Tested Hardware and OS List for a comprehensive list of supported operating systems. The LSI Logic* 53C1030 supports these PCI features:...
  • Page 62: Raid Functionality

    I/O Processor with XScale Technology in conjunction with the onboard LSI Logic* 53C1030 SCSI controller and resident RAID firmware on the server board. The RAID functionality is enabled by using the optional Intel® RAID Activation Key (1-wire serial security EEPROM) and dedicated RAID memory installed on Slot 2 (RAID DIMM). The system BIOS automatically detects the presence of the Intel RAID Activation Key and enables the ROMB subsystem (“IOP ROMB (SROMBU42E)
  • Page 63: Parallel Ata (Pata) Support

    3.4.4.1 RAID Memory Subsystem The Intel® Server Board SE7520AF2 includes a DDR DIMM socket (Slot 2 in the PCI slot area). This DIMM is not shared with main memory and is for exclusive use as RAID cache for ROMB functionality. The ROMB subsystem supports one 128 MB, 256 MB or 512 MB DDR333 un- buffered ECC DIMM, enabling higher performance operation (write back cache).
  • Page 64: Serial Ata (Sata) Support

    Intel RAID Technology implementation and provides the ability for an Intel® RAID Technology volume to be used as a boot disk as well as to detect any faults in the Intel® RAID Technology volume(s) attached to the Intel RAID controller.
  • Page 65: Video Controller

    3.4.7 Video Controller The Intel® Server Board SE7520AF2 provides an ATI* Rage XL PCI graphics accelerator with 8 MB of video SDRAM and support circuitry for an embedded SVGA video subsystem. The ATI* Rage XL chip contains a SVGA video controller, clock generator, 2D and 3D engine, and RAMDAC in a 272-pin PBGA.
  • Page 66: Table 21. Video Memory Interface

    Requests are serviced in a manner that ensures display integrity and maximum CPU/coprocessor drawing performance. The Intel® Server Board SE7520AF2 supports an 8MB (512Kx32bitx4 banks) SDRAM device for video memory. The following table shows the video memory interface signals: Table 21.
  • Page 67: Network Interface Controller (Nic)

    Figure 14. Video Controller PCI Bus Interface 3.4.8 Network Interface Controller (NIC) The Intel® Server Board SE7520AF2 supports a dual gigabit network interface controller, based ® on the Intel 82546GB. The 82546GB is a highly integrated PCI LAN controller in a 21 mm PBGA package.
  • Page 68: Usb 2.0 Support

    General Purpose Input/Output (GPIO) The National Semiconductor* PC87427 Super I/O provides general-purpose input/output pins that the Intel® Server Board SE7520AF2 utilizes. The following table identifies the pins and the signal names used in the schematic: Table 23. Super I/O GPIO Usage Table...
  • Page 69: Table 24. Serial A Header Pin-Out

    The floppy disk controller (FDC) in the SIO is functionally compatible with floppy disk controllers in the DP8473 and N844077. All FDC functions are integrated into the SIO including analog data separator and 16-byte FIFO. The Intel® Server Board SE7520AF2 provides access to the floppy interface via an SSI-compliant 36-pin connector.
  • Page 70: Bios Flash

    3.5.1 Memory Space At the highest level, the Intel “Nocona” processor address space is divided into four regions, as shown in the figure below. Each region contains subregions, as described in following sections. Attributes can be independently assigned to regions and subregions using the Intel® Server Board SE7520AF2 registers.
  • Page 71: Figure 14. Intel® Xeon Processor Memory Address Space

    640KB DOS Legacy 512KB Address Range Figure 15. Intel® Xeon Processor Memory Address Space 3.5.1.1 DOS Compatibility Region The first region of memory below 1 MB was defined for early PCs, and must be maintained for compatibility. The region is divided into subregions as shown in the following figure.
  • Page 72: Figure 15. Dos Compatibility Region

    Functional Architecture Intel® Server Board SE7520AF2 TPS 0FFFFFh System BIOS 0F0000h 0EFFFFh 960KB Extended System BIOS 0E0000h 0DFFFFh 896KB Add-in Card BIOS and Buffer Area 0C0000h 0BFFFFh 768KB PCI/ISA Video or SMM Area 0A0000h 09FFFFh 640KB ISA Window Area 080000h...
  • Page 73 3.5.1.2 Extended Memory Extended memory on Intel® Server Board SE7520AF2 is defined as all address space greater than 1MB. Extended memory region covers 8GB maximum of address space from addresses 0100000h to FFFFFFFh, as shown in the following figure. PCI memory space can be remapped to top of memory (TOM).
  • Page 74: Figure 16. Extended Memory Map

    Functional Architecture Intel® Server Board SE7520AF2 TPS 64GB ® Extended lntel E7520 Chipset Top of Memory (TOM) Region FFFFFFFFh High BIOS area FFE00000h PCI Memory Space FEC0FFFFh APIC space FEC00000h Top of Low Memory (TOLM) 512KB extended system Depends on installed DIMMs...
  • Page 75: Table 25. Smm Space Transaction Handling

    3.5.1.4 System Management Mode Handling The Intel® E7520 chipset supports System Management Mode (SMM) operation in one of three modes. System Management RAM (SMRAM) provides code and data storage space for the SMI_L handler code, and is made visible to the processor only on entry to SMM, or other conditions, which can be configured using Intel®...
  • Page 76: I/O Map

    3.5.2 I/O Map The Intel® Server Board SE7520AF2 allows I/O addresses to be mapped to the processor bus or through designated bridges in a multi-bridge system. Other PCI devices, including the ICH5- R, have built-in features that support PC-compatible I/O devices and functions, which are mapped to specific addresses in I/O space.
  • Page 77 Intel® Server Board SE7520AF2 TPS Functional Architecture Address (es) Resource Notes 0028h – 0029h Interrupt Controller 1 Aliased from 0020h – 0021h 002Ah – 002Bh 002Ch – 002Dh Interrupt Controller 1 Aliased from 0020h – 0021h 002Eh – 002Fh Super I/O (sIO) index and Data ports 0030h –...
  • Page 78: Accessing Configuration Space

    DMA Channel Stop Registers 051Ch Software NMI (051Ch) 0CF8h PCI CONFIG_ADDRESS Register 0CF9h Intel® Server Board SE7520AF2 Turbo and Reset Control 0CFCh PCI CONFIG_DATA Register 3.5.3 Accessing Configuration Space All PCI devices contain PCI configuration space, accessed using mechanism 1 defined in the PCI Local Bus Specification.
  • Page 79: Figure 17. Config_Addres Register

    (BSP) should perform PCI configuration space accesses. Precautions should be taken to guarantee that only one processor performs system configuration. Two Dword I/O registers in the Intel® E7520 chipset are used for the configuration space register access: CONFIG_ADDRESS (I/O address 0CF8h), CONFIG_DATA (I/O address 0CFCh).
  • Page 80: Hardware Initialization

    Functional Architecture Intel® Server Board SE7520AF2 TPS configuration cycles. The following table shows the correspondence between IDSEL values and PCI device numbers for the PCI bus. The lower 5-bits of the device number are used in CONFIG_ADDRESS bits [15::11]. Table 28. PCI Configuration IDs and Device Numbers...
  • Page 81: Clock Generation And Distribution

    Startup Inter Processor Interrupt (SIPI). The BSP begins by fetching the first instruction from the reset vector FFFFFFF0h. The Intel® E7520 chipset registers are updated to reflect memory configuration, all SDRAM is sized and initialized.
  • Page 82 Functional Architecture Intel® Server Board SE7520AF2 TPS DIF_2_P IOP332 DIF_2_N IOP332 DIF_3_P DIF_3_N DIF_4_P HP PCI Express* Slot 3 DIF_4_N HP PCI Express* Slot 3 DIF_5_P HP PCI Express* Slot 4 DIF_5_N HP PCI Express* Slot 4 DIF_6_P Pull-down DIF_6_N...
  • Page 83: Integrated Intel® Raid Controller Srombu42E

    IOP ROMB setup option in BIOS Setup. Figure 19. Intel® RAID Activation Key Note: The IOP ROMB option in BIOS Setup is grayed out unless a valid Intel® Activation Raid Key and compatible RAID memory are present. Primary Integrated Intel RAID Controller SROMBU42E Features Features of the integrated Intel®...
  • Page 84: Table 30. Integrated Intel® Raid Controller Srombu42E Features

    10 (mirroring and striping), and 50 (RAID 5 and striping) Advanced array configuration and management utilities Battery backup for up to 72 hours (requires use of the Intel® Portable Cache Module Accessory) Support for up to 14 SCSI drives per channel on storage system with SAF-TE...
  • Page 85: Configuration On Disk

    Configuration on Disk saves configuration information both in NVRAM on the Intel® RAID Controller SROMBU42E and on the disk drives attached to the controller. If the Intel® Server Board SE7520AF2 is replaced, the new board detects the RAID configuration from the configuration information on the drives.
  • Page 86: Raid Software Stack

    Intel® Server Board SE7520AF2 TPS RAID Software Stack The software described in this document is relevant to the integrated Intel® RAID Controller SROMBU42E functionality of the Intel® Server Board SE7520AF2, and is designated as Software Stack 2. This section describes the RAID controller, drive and array configuration, management utility operation, and drive installation.
  • Page 87: Raid Level Migration

    Intel® Server Board SE7520AF2 TPS Integrated Intel® RAID Controller SROMBU42E Drive coercion refers to the ability of the controller to recognize the size of the physical drives that are connected and then force the larger drives to use only the amount of space available on the smallest drive.
  • Page 88: Background Tasks

    Integrated Intel® RAID Controller SROMBU42E Intel® Server Board SE7520AF2 TPS Write Back - I/O completion is signaled when data is transferred to cache. Cache Policy Direct I/O - When possible, no cache is involved for both reads and writes. The data transfers will be directly from host to disk and from disk to host.
  • Page 89: Decoding An Audible Alarm

    4.3.7 Decoding an Audible Alarm The following list of beep tones is used on Intel RAID controllers using Software Stack 2. These beeps usually indicate that a drive has failed. Degraded Array - Short tone, 1 second on, 1 second off...
  • Page 90: Raid 1 - Disk Mirroring/Disk Duplexing

    Integrated Intel® RAID Controller SROMBU42E Intel® Server Board SE7520AF2 TPS 4.4.2 RAID 1 - Disk Mirroring/Disk Duplexing In RAID 1, all data is stored twice, once each on two identical hard disks making one drive a “mirror” image of the other. When one hard disk fails, all data is immediately available on the other without any impact on performance and data integrity.
  • Page 91: Raid 10 - Combination Of Raid 1 And Raid 0

    Intel® Server Board SE7520AF2 TPS Integrated Intel® RAID Controller SROMBU42E Figure 22. RAID 5 4.4.4 RAID 10 - Combination of RAID 1 and RAID 0 RAID 10 is a combination of RAID 0 (performance) and RAID 1 (data security). Unlike RAID 5, there is no need to calculate parity information.
  • Page 92: Levels Of Drive Hierarchy Within The Intel® Integrated Raid Firmware

    4.4.6 Levels of Drive Hierarchy within the Intel® Integrated RAID Firmware The Intel Integrated RAID firmware is based on three fundamental levels of hierarchy, as outlined below. Logical drives are created from drive arrays that are in turn created from physical drives.
  • Page 93: Intel® Raid Controller Drivers

    Hat* Linux 8.0 and 9.0, Red Hat* Enterprise Linux AS 2.1 and 3.0, and SuSE* Linux 8.0 and 8.2. With Web Console, you can perform the same tasks as with the BIOS Console. The Intel® RAID Web Console provides on-the-fly RAID migration, creating almost limitless adaptability and expansion of any logical drive while the system remains operational.
  • Page 94: Intel® Raid Bios Console Configuration Utility

    Integrated Intel® RAID Controller SROMBU42E Intel® Server Board SE7520AF2 TPS Choose a configuration method for physical arrays and logical disks Create drive arrays Define logical drives Initialize logical drives Access controller, logical drives, and physical arrays to display their properties...
  • Page 95: Screen And Option Descriptions

    Adapter Properties Screen When you select the Adapter Selection option on the main screen, BIOS Console displays a list of the Intel RAID adapters in the system. The Adapter Properties screen allows you to view and configure the software and hardware of the selected adapter.
  • Page 96 This option enables PCI delay transfers. Adapter BIOS This option enables the adapter BIOS. Set Factory Defaults This option loads the default Intel RAID BIOS Console CU settings. Auto Rebuild This option automatically rebuilds drives when they fail. Class Emulation Mode This option is preset for Mass Storage as class emulation mode.
  • Page 97 This option enables you to clear a configuration, create a new configuration, or add a configuration. The “Detailed Configuration Instructions” section provides detailed steps for using the Configuration Wizard. 4.7.3.7 Adapter Selection This option allows you to choose an Intel RAID adapter installed in the system. Revision 1.2 Intel order number C77866-003...
  • Page 98: Configuration Mismatch Screen

    Integrated Intel® RAID Controller SROMBU42E Intel® Server Board SE7520AF2 TPS Figure 26. Adapter Selection Screen 4.7.3.8 Physical View/Logical View Option This option toggles between Physical View and Logical View. 4.7.3.9 Exit This option allows you to exit and reboot the system.
  • Page 99: Figure 26. Configuration Wizard Screen

    Intel® Server Board SE7520AF2 TPS Integrated Intel® RAID Controller SROMBU42E 4.7.5.1 Configuration Wizard Start the Configuration Wizard by selecting the Configuration Wizard icon on the BIOS Console main screen. Figure 27. Configuration Wizard Screen Select Auto configuration with redundancy, Auto configuration without redundancy, or Custom configuration.
  • Page 100: Figure 27. Array Definition Screen

    Integrated Intel® RAID Controller SROMBU42E Intel® Server Board SE7520AF2 TPS Figure 28. Array Definition Screen 4.7.5.5 Configure the Logical Drive The logical drive parameters are the RAID level, stripe size, and read-ahead policy. Figure 29. Logical Drive Definition Revision 1.2...
  • Page 101 Intel® Server Board SE7520AF2 TPS Integrated Intel® RAID Controller SROMBU42E RAID Level – Choose the RAID level. Stripe Size – Specify the size of the segment written to each disk in a RAID configuration. You can set the stripe size to 4, 8, 16, 32, 64, or 128 Kbytes. The default is 64 Kbytes.
  • Page 102: Finish Configuration

    Integrated Intel® RAID Controller SROMBU42E Intel® Server Board SE7520AF2 TPS Select Size – Set the size of the logical drive in Mbytes. The right pane of the logical drive configuration window will list the maximum capacity that can be selected, depending on the RAID level chosen.
  • Page 103: Figure 30. Logic Drives Screen

    Intel® Server Board SE7520AF2 TPS Integrated Intel® RAID Controller SROMBU42E Figure 31. Logic Drives Screen Click the Home button to return to the main configuration screen. Select an additional logical drive to configure or exit the BIOS Console Configuration Utility and reboot the server system.
  • Page 104 Integrated Intel® RAID Controller SROMBU42E Intel® Server Board SE7520AF2 TPS < This page intentionally left blank. > Revision 1.2 Intel order number C77866-003...
  • Page 105: System Bios

    86B = Intel EPG 10A = Some OEM, etc. Figure 32. SE7520AF2 BIOS Identification String The system BIOS has the unique Board ID of “SE7520AF2”. The following is a sample production data string that is displayed during POST: SE7520AF20.86B.P01.01.00.0052.081320040715 Supported BIOS Features Table 35.
  • Page 106: Processor Initialization

    SSI Front Panel header ICMB/IPMB headers LCD header Floppy Processor Initialization The following section describes the memory initialization performed by the Intel® SE7520AF2 Server BIOS. 5.3.1 Multiple Processor Initialization IA32 processors have a microcode-based BSP-arbitration protocol. On reset, all of the processors compete to become the bootstrap processor (BSP).
  • Page 107: Mixed Processor Steppings

    Intel® Server Board SE7520AF2 TPS System BIOS The BSP is responsible for executing the BIOS power-on self-test (POST) and preparing the machine to boot the operating system. At boot time, the system is in virtual wire mode and the BSP alone is programmed to accept local interrupts (INTR driven by programmable interrupt controller (PIC) and non-maskable interrupt (NMI)).
  • Page 108: Microcode

    5.3.7 Microcode IA32 processors can correct specific errata through the loading of an Intel-supplied data block (i.e. microcode update). The BIOS is responsible for storing the update in nonvolatile memory and loading it into each processor during POST. The BIOS allows a number of microcode updates to be stored in the flash, limited by the amount of free space available.
  • Page 109: Memory Sizing

    For double-sided DIMMs, both rows are said to be present. Memory DIMMs must be populated in pairs. The Intel® Server Board SE7520AF2 has eight DIMM sockets, for four DIMM pairs. Both DIMMs in a pair must be identical (same manufacturer, CAS latency, number of rows, columns and devices, timing parameters etc.).
  • Page 110: Ecc Memory Initialization

    System BIOS Intel® Server Board SE7520AF2 TPS corresponding DIMM on other channel is copied to the spare DIMMs, which are put into service. The failing DIMMs are removed from service. The failure rate is preset in the BIOS and cannot be changed.
  • Page 111: Memory Error Handling

    Memory Error Handling The chipset detects and corrects single-bit memory errors and detects double-bit memory errors. The chipset supports Intel® x4 single device data correction (x4 SDDC) when in dual channel mode. Both single-bit and double-bit memory errors are reported to baseboard management by the BIOS, which handles SMI events generated by the MCH.
  • Page 112: Pci Initialization

    This option ROM space is also used by the console redirection binary (if enabled) and the user binary (if present and configured for run-time usage). The BIOS integrate option ROMs for the Intel® 82546GB Gb NIC, the ATI* Rage XL, and the LSI Logic* 53C1030 SCSI controller.
  • Page 113: Pci Apis

    Intel® Server Board SE7520AF2 TPS System BIOS 5.5.5 PCI APIs The system BIOS supports the INT 1Ah, AH = B1h functions as defined in the PCI BIOS Specification. The system BIOS supports the real mode interfaces and does not support the protected mode interfaces.
  • Page 114 The Intel® Server Board SE7520AF2 provides support for PCI Hot-Plug via the prescribed ACPI mechanism, through the use of SCIs and associated control methods via the PCI hot plug driver and GUI for insertion/removal/hot add request events.
  • Page 115: Table 38. Pci Express* Hot-Plug Led Function Table

    Intel® Server Board SE7520AF2 TPS System BIOS 3.3.8.3.2 PCI Hot-Plug Usage Model This section describes the hot-plug usage model for both the PCI Express* and PCI-X slots. Each of the four hot-plug slots has a set of status LEDs (for power and attention). The PCI hot plug GUI is used to invoke a hot-plug sequence to remove or add or replace an adapter via a software interface.
  • Page 116: Pci Express* Initialization

    System BIOS Intel® Server Board SE7520AF2 TPS 5.5.9 PCI Express* Initialization The following describes the PCI Express* initialization performed by the BIOS. 5.5.10 PCI Express* Enhanced Configuration Mechannisms The PCI Express* extends the configuration space to 4096 bytes per device/function as compared to 256 bytes allowed by PCI 2.3 configuration space.
  • Page 117: Removable Media Initialization

    The flash ROM contains system initialization routines, setup utility, and runtime support routines. The exact layout is subject to change, as determined by Intel. A 128 KB block is available for storing OEM code (user binary) and custom logos.
  • Page 118: System State Window

    System BIOS Intel® Server Board SE7520AF2 TPS 5.7.1 System State Window The top row of the screen is reserved for the system state window. On a graphics console, the row is 640x48. On a text console the row is 80x2.
  • Page 119: Quiet Boot / Oem Splash Screen

    <Esc> key while in Quiet Boot mode. If Quiet Boot is disabled, the BIOS displays diagnostic messages in place of the activity indicator and the splash screen. The BIOS allows OEMs to override the standard Intel logo with their own logo. 5.10 BIOS Boot Popup Menu The BIOS Boot Specification (BBS) provides for a Boot Menu Pop-up invoked by pressing the <ESC>...
  • Page 120: Console Redirection

    BIOS loads the default system configuration values during the next POST. When the Intel® Management Module is installed it provides two additional methods to issue a “reset system configuration” request. Using the front panel, the user can hold the reset button for 4 seconds and then press the power button while continuing to press the reset button.
  • Page 121: Entering Bios Setup

    Intel® Server Board SE7520AF2 TPS System BIOS Option Description Change Value The plus key on the keypad is used to change the value of the current menu item to the next value. This key scrolls through the values in the associated pick list without displaying the full list.
  • Page 122: Table 41. Bios Setup Advance Menu Options

    System BIOS Intel® Server Board SE7520AF2 TPS Feature Options Help Text Description Count Detected number of physical processors Installed Memory Size Amount of physical memory detected Server Board MCH Stepping Stepping Version of the Intel® E7520 MCH (C2 or C4)
  • Page 123 Intel® Server Board SE7520AF2 TPS System BIOS Feature Options Help Text Description Brand String Displays processor brand ID string Frequency Displays the calculated processor speed FSB Speed Displays the processor front- side bus speed. CPU 1 CPUID Displays the CPUID of the processor.
  • Page 124: Table 43. Bios Setup Ide Configuration Menu Options

    System BIOS Intel® Server Board SE7520AF2 TPS Feature Options Help Text Description Processor Retest Enabled If enabled, all processors will Rearms the processor sensors. be activated and retested on Only displayed if the Intel Disabled the next boot. This option will...
  • Page 125: Table 44. Bios Setup, Ide Device Configuration Sub-Menu Selections

    Intel® Server Board SE7520AF2 TPS System BIOS Secondary IDE Slave [Device Details] While entering setup, BIOS auto Selects submenu with additional detects the presence of IDE device details. Option displayed devices. This displays the grayed out and listing 'Not status of auto detection of IDE Detected' when in Enhanced devices.
  • Page 126: Table 45. Bios Setup Floppy Configuration Sub-Menu Selections

    System BIOS Intel® Server Board SE7520AF2 TPS Feature Options Help Text Description Type Not Installed Select the type of device connected The Auto setting will work in most to the system. cases. Auto CDROM ARMD LBA/Large Mode Disabled Disabled: Disables LBA Mode.
  • Page 127: Table 46. Bios Setup Superio Configuration Sub-Menu

    Intel® Server Board SE7520AF2 TPS System BIOS 5.11.5.1.5 SuperIO Configuration Sub-Menu Table 46. BIOS Setup SuperIO Configuration Sub-menu Feature Options Help Text Description Serial Port 1 Address Disabled Allows BIOS to Select Serial Port A Option that is used by other serial port Base Addresses.
  • Page 128: Table 48. Bios Setup, Usb Mass Storage Device Configuration Sub-Menu Selections

    System BIOS Intel® Server Board SE7520AF2 TPS 5.11.5.1.7 USB Mass-Storage Configuration Sub-Menu Table 48. BIOS Setup, USB Mass Storage Device Configuration Sub-menu Selections Feature Options Help Text Description USB Mass Storage 10 Sec Number of seconds POST waits for the USB Reset Delay mass storage device after start unit command.
  • Page 129: Table 50. Bios Setup, Memory Configuration Sub-Menu Selections

    Intel® Server Board SE7520AF2 TPS System BIOS Feature Options Help Text Description IOP ROMB Installed Intel RAID On Motherboard, Display only field, always (SROMBU42E) requires the use of the RAID grayed out. System BIOS will Not Installed Activation Key and a RAID...
  • Page 130 System BIOS Intel® Server Board SE7520AF2 TPS Feature Options Help Text Description DIMM 1B Installed Informational display. Not Installed Disabled Mirror Spare DIMM 2A Installed Informational display. Not Installed Disabled Mirror Spare DIMM 2B Installed Informational display. Not Installed Disabled...
  • Page 131: Table 51. Bios Setup, Boot Menu Selections

    Intel® Server Board SE7520AF2 TPS System BIOS Feature Options Help Text Description Memory Remap Feature Enabled Enable: Allow remapping of overlapped PCI memory above the Disabled total physical memory. Disable: Do not allow remapping of memory. Memory Mirroring / Sparing...
  • Page 132: Table 53. Bios Setup, Boot Device Priority Sub-Menu Selections

    System BIOS Intel® Server Board SE7520AF2 TPS Scan User Flash Area Allows BIOS to scan the Flash ROM for user Disabled binaries. Enabled 5.11.5.3.2 Boot Device Priority Sub-menu Table 53. BIOS Setup, Boot Device Priority Sub-menu Selections Feature Options Help Text...
  • Page 133: Table 57. Bios Setup, Security Menu Options

    Intel® Server Board SE7520AF2 TPS System BIOS nth Drive Varies Specifies the boot sequence from the available Varies based on system configuration. devices. 5.11.5.4 Security menu Table 57. BIOS Setup, Security Menu Options Feature Options Help Text Description Supervisor Install / Not installed Informational display.
  • Page 134: Table 58. Bios Setup, Server Menu Selections

    System BIOS Intel® Server Board SE7520AF2 TPS Secure Mode Boot When enabled, allows the host This node is grayed out if a user Disabled system to complete the boot password is not installed. Enabled process without a password. The keyboard will remain locked until a password is entered.
  • Page 135: Table 59. Bios Setup, System Management Sub-Menu Selections

    Intel® Server Board SE7520AF2 TPS System BIOS Feature Options Help Text Description Late POST Timeout Disabled This controls the time limit for add-in card detection. The system 5 minutes is reset on timeout. 10 minutes 15 minutes 20 minutes Hard Disk OS Boot Timeout...
  • Page 136: Table 60. Bios Setup Serial Console Features Sub-Menu Selections

    System BIOS Intel® Server Board SE7520AF2 TPS Secondary HSBP Revision Firmware revision of the Hot- (HSBP B) swap controller. Displays n/a if the controller is not present. 5.11.5.5.2 Serial Console features sub-menu selections Table 60. BIOS Setup Serial Console Features Sub-menu Selections...
  • Page 137: 5.12 Flash Architecture And Flash Update Utility

    The flash ROM contains system initialization routines, the BIOS Setup Utility, and runtime support routines. The exact layout is subject to change, as determined by Intel. A 64 KB user block is available for user ROM code or custom logos. The flash ROM also contains initialization code in compressed form for on-board peripherals, like SCSI, NIC and video controllers.
  • Page 138: 5.13 Rolling Bios And On-Line Updates

    The AMI FLASH update suite and Intel On-line updates preserve the existing BIOS image on the primary partition. BIOS updates are diverted to the secondary partition. After the update, a notification flag will be set.
  • Page 139 Intel® Server Board SE7520AF2 TPS System BIOS 5.14.1.1 In DOS − The flash bootable disk must have ROM image and AFUDOS.EXE. − Enter in DOS. − Run AFUDOS /i<ROM filename> [/n] [/p[b][n][c]]. 5.14.1.2 In Microsoft* Windows* − The flash disk must have ROM image, AMIFLDRV.SYS and AFUWIN.EXE.
  • Page 140: User Binary Area

    The BIOS has its ROM image size of 2 MB. A standard 1.44 MB floppy diskette cannot hold the ROM file due to the larger file size. The SE7520AF2 BIOS supports Rolling BIOS (see Rolling BIOS and On-line Updates section above for details) and contains a primary and secondary partition. The recovery process performs an update on the secondary partition in the same fashion that the normal flash update process updates the secondary partition.
  • Page 141: Update Oem Logo

    Intel® Server Board SE7520AF2 TPS System BIOS BIOS recovery can be used in one of the following devices: a USB Disk-On-Key, ATAPI CD- ROM/DVD, ATAPI ZIP drives, or a LS-120/LS-240 removable drive. The recovery disk must include the BIOS image file AMIBOOT.ROM.
  • Page 142: 5.15 Oem Binary

    ROMbuild.exe in DOS or WIN for updating the OEM logo. 5.15 OEM Binary The Intel® Server Board SE7520AF2 provides users with 16 KB of code and data for use during POST and at run-time. User binary code is executed at several defined hook points within the POST.
  • Page 143 Intel® Server Board SE7520AF2 TPS System BIOS The BIOS copies the user binary into system memory before the first scan point. If the user binary reports that it does not contain runtime code, it is located in conventional memory (0 - 640 KB).
  • Page 144: Scan Point Definitions

    System BIOS Intel® Server Board SE7520AF2 TPS ; to user binary extension structure ; Word Pointer to extension structure ; Reserved ; This is a list of 7 transfer addresses, one for each bit in the bitmap. ; 5 Bytes must be used for each.
  • Page 145: Format Of The Oem Binary Structure

    <Esc> key while in Quiet Boot mode. If Quiet Boot is disabled, BIOS displays diagnostic messages in place of the activity indicator and the splash screen. BIOS allows users to override the standard Intel logo with their own logo. 5.17 Operating System Boot, Sleep, and Wake 5.17.1...
  • Page 146: Operating System Boot, Sleep, And Wake

    The ACPI Description Tables are also provided by the ACPI BIOS. All IA32 server platforms support S0, S4, and S5 states. In addition to these, the Intel® Server Board SE7520AF2 also supports the S1 state. S1 and S4 are considered sleep states. The ACPI specification defines the sleep states and requires the system to support at least one of them.
  • Page 147: Sleep And Wake Functionality

    Intel® Server Board SE7520AF2 TPS System BIOS The system can wake from the S1 state using a PS/2 keyboard, mouse, and USB device in addition to the sources described above. The wake-up sources are enabled by the ACPI operating systems with co-operation from the drivers;...
  • Page 148: Sleep To On (Acpi)

    System BIOS Intel® Server Board SE7520AF2 TPS − ACPI S4 (suspend to disk) state − ACPI S5 (soft-off) state Table 65. Supported Wake Events Wake Event Supported via ACPI (by sleep state) Supported Via Legacy Wake Power Button Always wakes system...
  • Page 149: Platform Management

    Intel® Server Board SE7520AF2 TPS Platform Management Platform Management The Intel® Server Board SE7520AF2 has been designed to support different levels of platform management: Onboard Platform Instrumentation, optional Intel® Management Module – Professional Edition and Intel® Management Module – Advanced Edition.
  • Page 150: Table 66. Tiered Platform Management Feature Overview

    Platform Management Intel® Server Board SE7520AF2 TPS The following tables provide an overview of the features supported with each of the three management tiers: Table 66. Tiered Platform Management Feature Overview Onboard Platform Element Instrumentation Professional Advanced IPMI Messaging, Commands, and Abstractions...
  • Page 151: Table 67. Power And Reset Control

    Intel® Server Board SE7520AF2 TPS Platform Management Table 67. Power and Reset Control Source Power Cycle Power Up Power Down Hard Reset Pro/Adv Pro/Adv Pro/Adv Pro/Adv DPC (Serial) DPC (LAN) AC Power Restore IPMB ICMB PCI SMBus System Interface Watchdog Timer Expiration...
  • Page 152 1 – No SEL logging. The following diagram shows a Logical Block Diagram of the platform management architecture implemented on the Server Board SE7520AF2. Note: The interconnections and blocks shown are to illustrate the functional relationships between the system management elements, and do not map directly to the exact circuit implementation of the architecture.
  • Page 153: Standby

    Intel® Server Board SE7520AF2 TPS Platform Management FRONT PANEL Fault Power Temp Sensor Reset Power Front Panel Connector BASEBOARD PROC 1 & 2 - Therm Trip 1U PCI - IERR CPU 1&2 - Proc Hot - Temperature - VIDs - VRM Voltage...
  • Page 154: Ipmi Messaging, Commands, And Abstractions

    Platform Management Intel® Server Board SE7520AF2 TPS − Management controller (BMC and/or mBMC) and associated RAM, Flash, and SEEPROM which are used to monitor the various system power control sources including the front panel Power Button, the baseboard RTC alarm signal, and power on request messages from the auxiliary IPMB connector and PCI SMBus.
  • Page 155: Private Management Bus

    Intel® Server Board SE7520AF2 TPS Platform Management sensor access. The message-based interface isolates software from the particular hardware implementation. System Management Software discovers the platform’s sensor capabilities by reading the Sensor Data Records from a Sensor Data Record Repository managed by the management controller (i.e.
  • Page 156: Management Controllers

    Management Controllers At the heart of platform management is a management controller. To support the tiered management model, the Intel® Server Board SE7520AF2 supports two different management controllers. Integrated onto the baseboard is the National Semiconductor* 87431x Mini-BMC (mBMC) to provide the functionality of the onboard platform instrumentation management tier.
  • Page 157 − FRU Information Access. FRU (Field Replaceable Unit) information is non-volatile storage for serial number, part number, asset tag and other inventory information for the baseboard and chassis. The FRU implementation on SE7520AF2 includes write support for OEM-specific records. −...
  • Page 158: Onboard Platform Instrumentation Management Features And Functionality

    Platform Management Intel® Server Board SE7520AF2 TPS − Power Distribution Board (PDB) monitoring (Standard and Advanced systems only) − Updateable BMC Firmware − System Management Power Control (including providing Sleep/Wake and power push- button interfaces) − Platform Event Filtering (PEF) −...
  • Page 159: Mbmc Self-Test

    Intel® Server Board SE7520AF2 TPS Platform Management The following figure is a block diagram of the mBMC as it is used in a server management system. The external interface blocks to the mBMC are the discrete hardware peripheral device interface modules.
  • Page 160: Messaging Interfaces

    Platform Management Intel® Server Board SE7520AF2 TPS The mBMC communicates with the internal modules using its private SMBus. External devices and sensors interact with the mBMC using the peripheral SMBus. LOM communicates through the LOM SMBus. GPIO pins are available and are used for general input and output functions.
  • Page 161: Table 70. Supported Channel Assigments

    Intel® Server Board SE7520AF2 TPS Platform Management 6.2.4.1 Channel Management The mBMC supports two channels: System interface, and 802.3 LAN. Table 70. Supported Channel Assigments Channel Id Media type Supports Interface Sessions 802.3 LAN Interface IPMI-SMBus Multi sessions System Interface...
  • Page 162: Direct Platform Control (Ipmi Over Lan)

    Platform Management Intel® Server Board SE7520AF2 TPS implements gratuitous ARP support according to the Intelligent Platform Management Interface Specification v1.5. The Intelligent Platform Management Interface Specification v1.5 defines how IPMI messages, encapsulated in RMCP packet format, can be sent to and from the mBMC. This capability allows a remote console application to access the mBMC and perform the following operations: −...
  • Page 163 UDP port 26Fh is a ‘well known port’ address that is specified to carry RMCP formatted UDP datagrams. The on-board Intel network interface controllers contain circuitry that enables detecting and capturing RMCP packets that are received on Port 26Fh and making them available to the management controller via a ‘side-band’...
  • Page 164: Wake On Lan / Power On Lan And Magic Packet Support

    6.2.5.2 LAN Drivers and Setup The IPMI-over-LAN feature must be used with the appropriate Intel NIC Driver, and the NIC correctly configured in order for DPC LAN operation to occur transparently to the operating system and network applications. If an incorrect driver or NIC configuration is used, it is possible to get driver timeouts when the IPMI-over-LAN feature is enabled.
  • Page 165: Watchdog Timer

    Intel® Server Board SE7520AF2 TPS Platform Management 6.2.6.1 Wake On LAN in S4/S5 A configuration option is provided that allows the on-board NICs to be enabled to wake the system in an S4/S5 state, even if the operating system disabled Wake-On-LAN when it powered down the system.
  • Page 166: Sensor Data Record (Sdr) Repository

    Platform Management Intel® Server Board SE7520AF2 TPS If the RTC changes during system operation, system management software must synchronize the management controller time with the system time. If this is not done, the server should be reset so that BIOS will pass the new time to the mBMC.
  • Page 167: Table 73. Pef Action Priorities

    Intel® Server Board SE7520AF2 TPS Platform Management − Diagnostic Interrupt − Alert The mBMC maintains an Event Filter table with 30 entries that is used to select the actions to perform. Also maintained is a fixed/read-only Alert Policy Table entry. No alert strings are supported.
  • Page 168 Platform Management Intel® Server Board SE7520AF2 TPS Event Filter # Offset Mask Events Critical Proc 1-2 Thermal Trip, Config Error and IERR Deassert Degraded Proc 1-2 FRB3 Assert Degraded Proc 1-2 FRB3 Deassert Degraded Proc 1-2 Hot Assert Degraded Proc 1-2 Hot Deassert...
  • Page 169: Nmi Generation

    Intel® Server Board SE7520AF2 TPS Platform Management The user does not typically deal with filter contents directly. Instead, the Server Setup Utility provides a user interface that allows the user to select among a fixed set of pre-configured event filters.
  • Page 170: Platform Management Interconnects

    Platform Management Intel® Server Board SE7520AF2 TPS Platform Management Interconnects 6.3.1 Power Supply Interface Signals The mBMC supports two power supply control signals: Power On and Power Good. The Power On signal connects to the chassis power subsystem and is used to request power state changes (asserted = request Power On).
  • Page 171: System Reset Control

    Intel® Server Board SE7520AF2 TPS Platform Management 6.3.1.2 Power-down Sequence To power down the system, the mBMC effectively performs the sequence of power-up steps in reverse order. This operation can be initiated by one of the event occurrences listed in the following table and proceeds as follows: 1.
  • Page 172: Temperature-Based Fan Speed Control

    The management controller firmware expects to find an LM30 temperature sensor on the front panel board. Thus, the ambient temperature-based fan speed control capability is not enabled by default for SE7520AF2 as a baseboard-only product, but can be enabled via a management controller configuration change.
  • Page 173 Intel® Server Board SE7520AF2 TPS Platform Management deasserting SLEEP_S5 to the CPU configuration circuitry. If the configuration is good, PS_PWRON is asserted to the power supply. The supply then asserts POWERGOOD back to the mBMC. If the system is in Secure Mode or the Power Button is forced protected, then when the power switch is pressed, a Platform Security Violation Attempt event message is generated and no power control action is taken.
  • Page 174: Table 77. Chassis Id Leds

    The Identify signal state is preserved on Standby power across system power-on/off and system hard resets when an Intel Management Module is present. It is not preserved with the on-board platform instrumentation (mBMC and no IMM present) or when A/C power is removed.
  • Page 175: Fru Information

    6.3.4.6 Chassis Intrusion Switch The Intel® SE7520AF2 server platform supports chassis intrusion detection. The mBMC monitors the state of the Chassis Intrusion signal and makes the status of the signal available via the Get Chassis Status command and Physical Security sensor state. If enabled, a chassis intrusion state change causes the mBMC to generate a Physical Security sensor event message with a General Chassis Intrusion offset.
  • Page 176: Fru Information

    Platform Management Intel® Server Board SE7520AF2 TPS FRU information includes board serial number, part number, name, asset tag, and other information. FRUs that contain a management controller, use the controller to provide access to the FRU information. FRUs that lack a management controller can make their FRU information available via a SEEPROM directly connected to the mBMC’s sensor device private I...
  • Page 177: Table 79. Mbmc Built-In Sensors

    Intel® Server Board SE7520AF2 TPS Platform Management Event Triggers are ‘supported event generating offsets’ for discrete type sensors. The offsets can be found in the Generic Event/Reading Type Codes or Sensor Type Codes tables in the IPMI specification, depending on whether the sensor event/reading type is generic or a sensor specific response.
  • Page 178: Table 80. Intel® Server Board Se7520Af2 Sensors For Ob Platform Instrumentation Management

    Chassis Trig Offset Violation Intrusion Intrusion The following table shows the platform sensors that are supported by the mBMC. Table 80. Intel® Server Board SE7520AF2 Sensors for OB Platform Instrumentation Management Event / Sensor Event Offset Assert / Readable Sensor Name...
  • Page 179 Intel® Server Board SE7520AF2 TPS Platform Management Event / Sensor Event Offset Assert / Readable Sensor Name Reading Event Data Record Type Triggers Deassert Value/Offsets Action Type Type Voltage Threshold Fault LED BB +3.3V [u,l][ nr, c,nc] As & De...
  • Page 180: Table 81. Platform Sensors For The Intel® Management Module

    Analog Trig Offset Action The following table shows the platform sensors that are supported by the Intel® Management Module (IMM) Professional and Advanced Editions when installed on the Intel® Server Board SE7520AF2 and updated with SE7520AF2 platform specific firmware. Table 81. Platform Sensors for the Intel® Management Module...
  • Page 181 Intel® Server Board SE7520AF2 TPS Platform Management Event / Readable Event Offset Assert / Sensor Name Sensor Type Reading Value / EventData Triggers Deassert Type Offsets Redundancy Regained Redundancy lost Redundancy Degraded Non-red:Suff res from redund Power Unit Power Unit...
  • Page 182 Platform Management Intel® Server Board SE7520AF2 TPS Event / Readable Event Offset Assert / Sensor Name Sensor Type Reading Value / EventData Triggers Deassert Type Offsets 00: Session Sensor Activation Session Audit As defined Session Audit Specific – by IPMI...
  • Page 183 Intel® Server Board SE7520AF2 TPS Platform Management Event / Readable Event Offset Assert / Sensor Name Sensor Type Reading Value / EventData Triggers Deassert Type Offsets Threshold Tach Fan 6 [u,l][nr,c,nc] As & De Analog R, T – Redundancy Regained...
  • Page 184 Platform Management Intel® Server Board SE7520AF2 TPS Event / Readable Event Offset Assert / Sensor Name Sensor Type Reading Value / EventData Triggers Deassert Type Offsets Power Nozzle Current Threshold [u,l][ nr,c,nc] As & De Analog R, T – Power Supply 2...
  • Page 185 Intel® Server Board SE7520AF2 TPS Platform Management Event / Readable Event Offset Assert / Sensor Name Sensor Type Reading Value / EventData Triggers Deassert Type Offsets Digital SMI Signal State Discrete State Asserted – – – – – IERR Thermal Trip...
  • Page 186 Platform Management Intel® Server Board SE7520AF2 TPS Event / Readable Event Offset Assert / Sensor Name Sensor Type Reading Value / EventData Triggers Deassert Type Offsets Voltage Threshold Processor 1 Vcc [u,l][ nr,c,nc] As & De Analog R, T –...
  • Page 187 Intel® Server Board SE7520AF2 TPS Platform Management Event / Readable Event Offset Assert / Sensor Name Sensor Type Reading Value / EventData Triggers Deassert Type Offsets Fault Status Asserted Sensor Device Installed Slot Connector DIMM 7 Specific – Trig Offset –...
  • Page 188 Platform Management Intel® Server Board SE7520AF2 TPS Event / Readable Event Offset Assert / Sensor Name Sensor Type Reading Value / EventData Triggers Deassert Type Offsets Fully Redundant DIMM Domain 2 Memory Discrete Non-red:Suff res Sparing – Trig Offset –...
  • Page 189: Error Reporting And Handling

    This section covers general information regarding Error reporting, error logging and handling by BIOS and firmware. The BIOS of the Intel® Server Board SE7520AF2 indicates the current testing phase during POST by writing a hex code to I/O location 80h. If errors are encountered, error messages or codes will either be displayed to the video screen, or if an error has occurred prior to video initialization, errors will be reported through a series of audio beep codes.
  • Page 190: Frb-1 - Bsp Self-Test Failures

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS Options are provided by the BIOS to control the policy applied to FRB-2 failures. By default, an FRB-2 failure results in the failing processor being disabled during the next reboot. This policy can be overridden to prevent BSP from ever being disabled due to the FRB-2 failure or a policy resulting in disabling the BSP after three consecutive FRB-2 failures can be selected.
  • Page 191: Ap Failures

    Intel® Server Board SE7520AF2 TPS Error Reporting and Handling disabled regardless of option settings. Otherwise, if the system hangs during POST, before the BIOS disables the timer, the BMC generates an asynchronous system reset (ASR). The BMC retains status bits that can be read by BIOS later in the POST for the purpose of disabling the previously failing processor, logging the appropriate event into the SEL, and displaying an appropriate error message to the user.
  • Page 192: Error Logging

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS Three states are possible for each processor slot: 1. Processor installed (status only, indicates processor has passed BIOS POST). 2. Processor failed. The processor may have failed FRB-2, FRB-3, or BIST, and it has been disabled.
  • Page 193 Intel® Server Board SE7520AF2 TPS Error Reporting and Handling and SERR# through NMI. Disabling NMI for PERR# and/or SERR# also disables logging of the corresponding event. In the case of PERR#, the PCI bus master has the option to retry the offending transaction, or to report it using SERR#.
  • Page 194: Table 82. Memory Error Events

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS 7.2.2.6 Boot Event The BIOS downloads the system date and time to the BMC during POST and logs a boot event. This record does not indicate an error, and software that parses the event log should treat it as such.
  • Page 195: Table 83. Examples Of Event Data Field Contents For Memory Errors

    Intel® Server Board SE7520AF2 TPS Error Reporting and Handling Field IPMI definition BIOS-Specific Implementation Event Data 1 00 = unspecified byte 2 Follow IPMI definition. If either of the two data bytes following this do not have any data, that byte should be set 10 = OEM code in byte 2.
  • Page 196: Table 85. Event Data Field Contents For Pci Errors

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS Event Data 1 7:6 00 = unspecified byte 2; 10 = OEM Follow IPMI definition. code in byte 2. If either of the two data bytes following this do not have 5:4 00 = unspecified byte 3;...
  • Page 197: Bios Generated Ipmi Events

    Intel® Server Board SE7520AF2 TPS Error Reporting and Handling Sensor number Number of sensor that generated this event Unique value for each type of event because IPMI specification requires that. This field has no other significance, and it should not be displayed to the end user if the event is logged by BIOS.
  • Page 198: Single Bit Ecc Error Throttling Prevention

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS Synrome Memory Data2: Uncorrectabl DIMM e ECC location Data3: Synrome POST Data2[0: A0h or See POST POST Error Error Data2 error code table7.3.3. Data2:low byte Data3:hig h byte System Data2: Timestamp...
  • Page 199: Error Messages And Error Codes

    Intel® Server Board SE7520AF2 TPS Error Reporting and Handling error handler disables further reporting of that type of error. A unique counter is used for each type of error; i.e., an overrun of memory errors does not affect bus error reporting.
  • Page 200: Table 90. Post Code Checkpoints

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS DIAGNOSTIC LEDS Figure 41. Location of Diagnostic LEDs on Baseboard 7.3.1.3 POST Code Checkpoints The following table describes the type of checkpoints that may occur during the POST portion of the BIOS.
  • Page 201 Intel® Server Board SE7520AF2 TPS Error Reporting and Handling Diagnostic LED Description Decoder Check G=Green, R=Red, point A=Amber Re-enable cache for boot strap processor Early CPU Init Exit Initializes the 8042 compatible Key Board controller. Detects the presence of PS/2 mouse.
  • Page 202: Table 91. Bootblock Initialization Code Checkpoints

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS Diagnostic LED Description Decoder Check G=Green, R=Red, point A=Amber Late POST initialization of chipset registers. Build ACPI tables (if ACPI is supported) Program the peripheral parameters. Enable/Disable NMI as selected Late POST initialization of system management interrupt.
  • Page 203: Table 92. Bootblock Recovery Code Checkpoints

    Intel® Server Board SE7520AF2 TPS Error Reporting and Handling Diagnostic LED Description Decoder Check G=Green, R=Red, point A=Amber Disable CACHE before memory detection. Execute full memory sizing module. Verify that flat mode is enabled. If memory sizing module not executed, start memory refresh and do memory sizing in Bootblock code.
  • Page 204: Table 93. Dim Code Checkpoints

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS Diagnostic LED Description Decoder Check G=Green, R=Red, point A=Amber Disable ATAPI hardware. Jump back to checkpoint E9. Read error occurred on media. Jump back to checkpoint EB. Search for pre-defined recovery file name in root directory.
  • Page 205: Table 94. Acpi Runtime Checkpoints

    Intel® Server Board SE7520AF2 TPS Error Reporting and Handling While control is in the different functions, additional checkpoints are output to port 80h as a word value to identify the routines under execution. The low byte value indicates the main POST Code Checkpoint.
  • Page 206: Bios Messages

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS First ASL check point. Indicates the system is running in ACPI mode. System is running in APIC mode. 01, 02, 03, 04, 05 Entering sleep state S1, S2, S3, S4, or S5.
  • Page 207: Table 97. Storage Device Bios Messages

    Intel® Server Board SE7520AF2 TPS Error Reporting and Handling B: Drive Error The BIOS attempted to configure the B: drive during POST, but was unable to properly configure the device. This may be due to a bad cable or faulty diskette drive.
  • Page 208 Error Reporting and Handling Intel® Server Board SE7520AF2 TPS Master Hard Disk Error The IDE/ATAPI device configured as Master in the 5th IDE controller could not be properly initialized by the BIOS. This message is typically displayed when the BIOS is trying to detect and configure IDE/ATAPI devices in POST.
  • Page 209: Table 98. Virus Related Bios Messages

    Intel® Server Board SE7520AF2 TPS Error Reporting and Handling Master Drive - ATAPI Incompatible The IDE/ATAPI device configured as Master in the 5 IDE controller failed an ATAPI compatibility test. This message is typically displayed when the BIOS is trying to detect and configure IDE/ATAPI devices in POST.
  • Page 210: Table 99. System Configuration Bios Messages

    Microcode Error BIOS could not find or load the CPU Microcode Update to the CPU. This message only applies to INTEL CPUs. The message is most likely to appear when a brand new CPU is installed in a motherboard with an outdated BIOS.
  • Page 211: Table 100. Cmos Bios Messages

    Intel® Server Board SE7520AF2 TPS Error Reporting and Handling Timer Error Indicates an error while programming the count register of channel 2 of the 8254 timer. This may indicate a problem with system hardware. Interrupt Controller-1 error BIOS POST could not initialize the Master Interrupt Controller.
  • Page 212: Post Error Messages And Handling

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS Message Displayed Description Warning! Unsupported USB device found and disabled! This message is displayed when a non-bootable USB device is enumerated and disabled by the BIOS. Warning! Port 60h/64h emulation is not supported by this...
  • Page 213 Intel® Server Board SE7520AF2 TPS Error Reporting and Handling Error Code Error Message Response 0040 Refresh timer test failed Halt 0044 DMA Controller Error Halt 0045 DMA-1 Error Halt 0046 DMA-2 Error Halt 0048 Password check failed Halt 004C Keyboard/Interface Error...
  • Page 214: Table 105. Management Module Post Error Codes And Messages

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS Error Code Error Message Response 8180 BIOS does not support current stepping for Processor 1 Pause 8181 BIOS does not support current stepping for Processor 2 Pause 8190 Watchdog timer failed on last boot...
  • Page 215: Boot Block Error Beep Codes

    Intel® Server Board SE7520AF2 TPS Error Reporting and Handling 00150100 Multi-bit error occurred: forcing NMI DIMM = ?? DIMM = ?? ( could not isolate) DIMM D?? is Disabled. 00150900 SERR/PERR Detected on PCI bus ( no source found )
  • Page 216: Post Error Pause" Option

    Error Reporting and Handling Intel® Server Board SE7520AF2 TPS Number of Beeps Description Memory refresh timer error Parity error in base memory (first 64KB block) Base memory read / write test error Motherboard timer not operational Processor error 8042 Gate A20 test error (cannot switch to protected mode)
  • Page 217: Connectors, Headers And Jumpers

    Board Connector Information The following section provides detailed information regarding all connectors, headers and jumpers on the Server Board SE7520AF2. Table 109 lists all connector types available on the board and corresponding reference designators printed on silkscreen. Table 109. Board Connector Matrix...
  • Page 218: Main Power Connector

    Connectors, Headers and Jumpers Intel® Server Board SE7520AF2 TPS HSBP J1K1, J1K2 Header Recovery Jumpers J1D1 Jumper Main Power Connector The main power supply connection is obtained using the 24-pin connector. The following table defines the pin-outs of the connector.
  • Page 219: Main Memory Module Connector

    +12Vdc Yellow Main Memory Module Connector The Intel® Server Board SE7520AF2 has eight DIMM connectors which support registered ECC DDR-2 400MHz modules. For additional DIMM information, refer to the DDR2-400Mhz Registered DIMM Specification. Table 113. DIMM Connectors (J9D1, J9D2, J8D2, J8D3, J7D3, J8D1, J7D1, J7D2)
  • Page 220: Raid Memory Module Connector

    DQ59 VDDSPD RAID Memory Module Connector The Intel® Server Board SE7520AF2 has one RAID DIMM connector (Slot 2) which supports one unbuffered ECC DDR 333 MHz module. For additional DIMM information, refer to the DDR 333Mhz Registered DIMM Specification. Table 114. RAID DIMM Connector (J1D5)
  • Page 221: Processor Socket

    DQ30 VDDQ DQ24 DQ52 Processor Socket The SE7520AF2 has two Socket 604 processor sockets. The following table provides the processor socket pin numbers and pin names: Table 115. Socket 604 Processor Socket Pinout (J8H1, J6H1) Pin Name Pin Name Pin Name...
  • Page 222 Connectors, Headers and Jumpers Intel® Server Board SE7520AF2 TPS Pin Name Pin Name Pin Name Pin Name Pin Name A14# A10# DEFER# REQ0# VID0 Reserved Reserved REQ1# IGNNE# BPM3# LOCK# REQ4# SMI# BPM0# LINT0 VID1 VPM1# PROCHOT# BPM5# GTLREF IERR#...
  • Page 223 Intel® Server Board SE7520AF2 TPS Connectors, Headers and Jumpers Pin Name Pin Name Pin Name Pin Name Pin Name AC11 D43# AD21 D29# AC12 D41# AD22 DBI1# BSEL1 AC13 AD23 VCCA AC14 D50# AD24 D21# Reserved AC15 DP2# AD25 D18#...
  • Page 224: Table 116. Imm Connector Pin-Out (J3J1)

    AD20 Note: These are “Reserved” pins on the Intel® Xeon™ processor. In systems utilizing the Intel® Xeon™ processor, the system designer must terminate these signals to the processor Vcc. Base boards treating AA3 and AB3 as Reserved will operate correctly with a bus clock of 100MHz System Management Headers 8.6.1...
  • Page 225: System Management Headers

    Intel® Server Board SE7520AF2 TPS Connectors, Headers and Jumpers FMC Signal Name FMC Pin Description DVI_TX2M Red TMDS differential DVI output of graphics chip DVI_CLK_TX1CP TMDS differential DVI clock output of graphics chip DVI_TX2P Red TMDS differential DVI output of graphics chip...
  • Page 226 Connectors, Headers and Jumpers Intel® Server Board SE7520AF2 TPS FMC Signal Name FMC Pin Description SMB_I2C_3VSB_SDA This bus should connect to the PCI slots, ICH, and mBMC (host I/F). An isolated version of this bus (non-Standby) should connect to the...
  • Page 227: Icmb Header

    Intel® Server Board SE7520AF2 TPS Connectors, Headers and Jumpers FMC Signal Name FMC Pin Description CPU1_SKTOCC_N Indicates that a processor is in the primary processor socket. If this socket is detected empty and there’s an attempt to power up the...
  • Page 228: Ipmb Header

    Local I2C SDA BMC IMB 5 V Standby Data Line Local I2C SCL BMC IMB 5 V Standby Clock Line Note: IPMB bus is only available when an Intel® Management Module (Professional or Advanced) is present. 8.6.4 OEM RMC Header Table 119.
  • Page 229: Pci Slot Connector

    GND – HSBP_B PCI Slot Connector The Intel® SE7520AF2 Server Board enables 5 PCI expansion slots: Slot 1 (PCI-X 64/133), Slot 3 (PCI Exp x4), Slot 4 (PCI Exp x8), Slot 5 (PCI-X 64/133), Slot 6 (PCI-X 64/100). The PCI Express* slots both are enabled with a x8 physical connector, although only Slot 4 has a x8 interface (Slot 3 has a x4 interface).
  • Page 230: Table 123. Slot 3 And 4 Pci Express* Pin-Out (J2C1, J3C1)

    Connectors, Headers and Jumpers Intel® Server Board SE7520AF2 TPS Side B Side A Side B Side A AD[31] AD[30] C/BE[4]# +3.3 V AD[29] +3.3 V Ground PAR64 Ground AD[28] AD[63] AD[62] AD[27] AD[26] AD[61] Ground AD[25] Ground +3.3 V AD[60] +3.3 V...
  • Page 231: Table 124. Slot 6 Pci-X 64-Bit 3.3V Pin-Out (J4D2, Riser Capable)

    Intel® Server Board SE7520AF2 TPS Connectors, Headers and Jumpers Side B Side A Side B Side A Connector Key Connector Key PETp5 Ground RSVD Ground PETn5 Ground Ground REFCLK+ Ground PERp5 PETp0 REFCLK- Ground PERn5 PETn0 Ground PETp6 Ground Ground...
  • Page 232: Front Panel Connectors

    Connectors, Headers and Jumpers Intel® Server Board SE7520AF2 TPS Side B Side A Side B Side A AD[25] Ground +3.3 V AD[60] +3.3 V AD[24] AD[59] AD[58] C/BE[3]# IDSEL AD[57] Ground AD[23] +3.3 V Ground AD[56] Ground AD[22] AD[55] AD[54]...
  • Page 233: Vga Connector

    DDCCLK 8.10 SCSI Connector The Intel® Server Board SE7520AF2 provides two internal wide SCSI connectors (Channel A = J1H1, Channel B = J1F1). The following table details the pin-out of the SCSI connectors. Table 127. 68-pin SCSI Connector Pin-out (J1H1, J1F1)
  • Page 234: 8.11 Nic Connectors

    +DB(11) -DB(11) 8.11 NIC Connectors The Intel® Server Board SE7520AF2 provides two Gigabit network interfaces using two stacked identical RJ45 connectors. The following table details the pin-out of each connector. Table 128. NIC1 and NIC2 1.0Gb RJ45 Connector Pin-out (J6A1)
  • Page 235: 8.12 Ata Connector

    IDE_HD_ACT_L 8.13 USB Connector The Intel® Server Board SE7520AF2 supports three USB connectors, which are stacked in a single housing. The pin-out for each connector is identical and is detailed in the following table. Table 130. USB Connectors Pin-out (J9A2) Signal Name USB_PWR<0>...
  • Page 236: 8.14 Floppy Connector

    Front Panel USB Overcurrent signal. This signal is not used 8.14 Floppy Connector The Intel® Server Board SE7520AF2 provides a standard 34-pin interface to the floppy drive controller. The following tables detail the pin-out of the 34-pin legacy floppy connector.
  • Page 237: Table 133. Rear Db-9 Serial A Port Pin-Out (J8A1)

    FD_DSKCHG_L 8.15 Serial Port Connector The SE7520AF2 supports two serial ports: A DB-9 connector located on the back I/O area of the baseboard enabling Serial Port A A 9-pin DH-10 header on the server board (J1B1) enables an optional Serial Port B...
  • Page 238: Serial Port Connector

    KBCLK MSCLK 8.17 Fan Headers The Intel® Server Board SE7520AF2 provides eight fan headers: two for CPU fans and six for system fans. The CPU fans are labeled “CPU1_FAN” and “CPU2_FAN”. The CPU fan connectors only support steady 12-volt power.
  • Page 239: Fan Headers

    Intel® Server Board SE7520AF2 TPS Connectors, Headers and Jumpers Signal Name Type Description Ground Power GROUND is the power supply ground Fan Power Power Variable Speed Fan Power Fan Tach FAN_TACH signal is connected to the BMC to monitor the FAN speed...
  • Page 240: Configuration Jumpers

    This section describes configuration jumper options on the Server Board SE7520AF2. System Recovery and Update Jumpers The Intel® Server Board SE7520AF2 provides an 11-pin single inline header (J1D1), located on the edge of the baseboard next to the Front Panel connector, this connector provides a total of three 3-pin jumper blocks that are used to configure several system recovery and update options.
  • Page 241: Rolling Bios Bank Selection Jumper

    Rolling BIOS Bank Selection Jumper The Intel® Server Board SE7520AF2 provides a 3-pin header (J2J6), located next to the SATA headers on the board to provide the option to force the board to boot from Bank 0 as part of the Rolling BIOS feature.
  • Page 242: General Specifications

    10.3 Processor Power Support The SE7520AF2 is designed to support the Thermal Design Point (TDP) guideline for Intel® Xeon™ processors. In addition, the Flexible Motherboard Guidelines (FMB) have been followed to help determine the suggested thermal and current design values for anticipating future processor needs.
  • Page 243: Processor Power Support

    If the values found in the EMTS are different then those published here, the EMTS values will supersede these, and should be used. 10.4 SE7520AF2 Power Budget The following section describes the power consumption of the Intel® Server Board SE7520AF2. Table 144. SE7520AF2 Power Budget +3.3V...
  • Page 244: Se7520Af2 Power Budget

    General Specifications Intel® Server Board SE7520AF2 TPS reach regulation within 50 ms (T ) of each other and begin to turn off within 400 ms (T vout_on vout_off of each other. The following figure shows the output voltage timing parameters.
  • Page 245 Intel® Server Board SE7520AF2 TPS General Specifications T pson_pwok Delay from PSON# deactive to PWOK being de-asserted. msec Tpwok_on Delay from output voltages within regulation limits to PWOK asserted at 1000 msec turn on. T pwok_off Delay from PWOK de-asserted to output voltages (3.3V, 5V, 12V, -12V) msec dropping out of regulation limits.
  • Page 246: Voltage Recovery Timing Specifications

    General Specifications Intel® Server Board SE7520AF2 TPS Voltage shall remain within +/- 5% of the nominal set voltage on the +5 V, +12 V, 3.3 V, - 5 V and -12 V output, during instantaneous changes in load shown in the following table.
  • Page 247 Intel® Server Board SE7520AF2 TPS General Specifications <This page intentionally left blank> Revision 1.2 Intel order number C77866-003...
  • Page 248 11.1.2 Product EMC Compliance The SE7520AF2 has been has been tested and verified to comply with the following electromagnetic compatibility (EMC) regulations when installed in a compatible Intel host system. For information on compatible host system(s), contact your local Intel representative.
  • Page 249: Product Regulatory Compliance

    Intel® Server Board SE7520AF2 TPS Product Regulatory Compliance 11.2 Electromagnetic Compatibility Notices 11.2.1 FCC (USA) This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
  • Page 250: Australian Communications Authority (Aca) (C-Tick Declaration Of Conformity)251

    Product Regulatory Compliance Intel® Server Board SE7520AF2 TPS 11.2.4 Australian Communications Authority (ACA) (C-Tick Declaration of Conformity) This product has been tested to AS/NZS 3548, and complies with ACA emission requirements. The product has been marked with the C-Tick mark to illustrate its compliance.
  • Page 251 Intel® Server Board SE7520AF2 TPS Product Regulatory Compliance ADVARSEL Lithiumbatteri - Eksplosjonsfare. Ved utskifting benyttes kun batteri som anbefalt av apparatfabrikanten. Brukt batteri returneres apparatleverandøren. VARNING Explosionsfara vid felaktigt batteribyte. Använd samma batterityp eller en ekvivalent typ som rekommenderas av apparattillverkaren. Kassera använt batteri enligt fabrikantens instruktion.
  • Page 252: Integration And Usage Tips

    Integration and Usage Tips Integration and Usage Tips This section provides a bullet list of useful information that is unique to the Intel® Server Board SE7520AF2 and should be kept in mind while assembling and configuring your SE7520AF2 based server.
  • Page 253: Glossary

    Glossary Intel® Server Board SE7520AF2 TPS Glossary Term Definition ACPI Advanced Configuration and Power Interface ANSI American National Standards Institute Application processor ASIC Application Specific Integrated Circuit Asynchronous Reset Ball-grid Array BIOS Basic input/output system BIST Built-in self test Server board Management Controller Bridge Circuitry connecting one computer bus to another, allowing an agent on one to access the other.
  • Page 254 Intel® Server Board SE7520AF2 TPS Glossary Term Definition Keyboard Controller Style Local area network Logical Block Address Liquid crystal display Low pin count Least Significant Bit Low-Voltage Differential 1024 KB Multi-Bit Error milliseconds Most Significant Bit MT/s Mega transfers per second...
  • Page 255 Glossary Intel® Server Board SE7520AF2 TPS Term Definition System Event Log SERIRQ Serialized Interrupt Requests SERR System Error Server Management Server management interrupt. SMI is the highest priority nonmaskable interrupt System Management Mode System Management Software SNMP Simple Network Management Protocol...
  • Page 256: Reference Specifications And Documents

    Mini BMC Core External Product Specification. Intel Corporation Sahalee Baseboard Management Controller Core External Product Specification (Sahalee BMC Core EPS for IPMI 2.0 Systems), Intel Corporation. Sahalee Platform Information Area External Product Specification (Sahalee PIA EPS) ver 1.0, Intel Corporation Server Chassis SC5300 Technical Product Specification, Intel Corporation.

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