Error Reporting And Handling; Fault Resilient Booting (Frb); Frb-3 - Bsp Reset Failures; Frb-2 - Bsp Post Failures - Intel SE7520AF2 Technical Product Specification

Intel® Server Board SE7520AF2 TPS
7.

Error Reporting and Handling

This section covers general information regarding Error reporting, error logging and handling by
BIOS and firmware.
The BIOS of the Intel® Server Board SE7520AF2 indicates the current testing phase during
POST by writing a hex code to I/O location 80h. If errors are encountered, error messages or
codes will either be displayed to the video screen, or if an error has occurred prior to video
initialization, errors will be reported through a series of audio beep codes.
The error codes are defined by Intel and whenever possible are backward compatible with error
codes used on earlier platforms.
7.1

Fault Resilient Booting (FRB)

It should be noted that processors will not be disabled if the system is using the mBMC, this
advanced resilience server feature is only available with an Intel® Management Module
installed.
7.1.1 FRB-3 – BSP Reset Failures
The BIOS and firmware provides a feature to guarantee that the system boots, even if one or
more processors fail during POST. The BMC contains two watchdog timers that can be
configured to reset the system upon time-out. The first timer (FRB-3) starts counting down
whenever the system comes out of hard reset. If the Boot Strap Processor (BSP) successfully
resets and begins executing, the BIOS disables the FRB-3 timer in the BMC and the system
continues executing POST. If the timer expires because of the BSP's failure to fetch or execute
BIOS code, the BMC resets the system and disables the failed processor. The BMC continues
to change the bootstrap processor until the BIOS successfully disables the FRB-3 timer. The
BMC sounds beep codes on the system speaker, if it fails to find a good processor. It will
continue to cycle until it finds a good processor. The process of cycling through all the
processors is repeated upon system reset or power cycle. Soft resets do not affect the FRB-3
timer. The duration of the FRB3 timer is set by system firmware. The mBMC also supports the
algorithm described above, with the exception that it does not disable the processor.
7.1.2 FRB-2 – BSP POST Failures
The second timer (FRB-2) is set to several minutes by BIOS and is designed to guarantee that
the system completes POST. The FRB-2 timer is enabled just before the FRB-3 timer is
disabled to prevent any "unprotected" window of time. Near the end of POST, the BIOS disables
the FRB-2 timer. If the system contains more than 1 GB of memory and the user chooses to test
every DWORD of memory, the watchdog timer is extended before the extended memory test
starts, because the memory test can exceed the timer duration. The BIOS will also disable
watchdog timer before prompting the user for a boot password. If the system hangs during
POST, before the BIOS disables the FRB-2 timer, the BMC generates an asynchronous system
reset (ASR). The BMC retains status bits that can be read by BIOS later in the POST for the
purpose of disabling the previously failing processor, logging the appropriate event into the
System Event Log (SEL), and displaying an appropriate error message to the user.
Revision 1.2
Intel order number C77866-003
Error Reporting and Handling
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