Table 19. Interrupt Definitions - Intel SE7520AF2 Technical Product Specification

Intel® Server Board SE7520AF2 TPS
3.4.2.3 Legacy Interrupt Sources
The table below recommends the logical interrupt mapping of interrupt sources on the Intel®
Server Board SE7520AF2. The actual interrupt map is defined using configuration registers in
the ICH5-R.
ISA
Interrupt
IRQ0 Timer/counter, HPET #0 in legacy replacement Mode. In APIC mode, cascade from 8259 controller 1
IRQ1 Keyboard
IRQ2 Slave controller INTR output.. In APIC mode Timer/counter, HPET#0
IRQ3 Serial port A
IRQ4 Serial port B
IRQ5 Parallel Port
IRQ6 Floppy
IRQ8 RTC/HPET#1 in legacy replacement mode
IRQ9 Generic, Option for SCI
IRQ10 Generic, Option for SCI
IRQ11 HPET#2, option for SCSI, TCO*
IRQ12 PS2 Mouse
IRQ13 FERR
IRQ14 Primary ATA, legacy mode
PIRQA USB 1.1 controller 1 and 4
PIRQB Video
PIRQC USB 1.1 controller 3, Native IDE, SATA
PIRQD USB 1.1 controller 2
PIRQE Option for SCI, TCO, HPET#0,1,2
PIRQF Option for SCI, TCO, HPET#0,1,2
PIRQG Option for SCI, TCO, HPET#0,1,2
PIRQH USB 2.0 EHCI controller 1, Option for SCI, TCO, HPET#0,1,2
Ser IRQ SIO3
3.4.2.4 Serialized IRQ Support
The Intel® Server Board SE7520AF2 supports a serialized interrupt delivery mechanism.
Serialized Interrupt Requests (SERIRQ) consists of a start frame, a minimum of 17 IRQ / data
channels, and a stop frame. Any slave device in the quiet mode may initiate the start frame.
While in continuous mode, the start frame is initiated by the host controller.
3.4.2.5 IRQ Scan for PCIIRQ
The IRQ / data frame structure includes the ability to handle up to 32 sampling channels with
the standard implementation using the minimum 17 sampling channels. The Intel® Server
Board SE7520AF2 has an external PCI interrupt serializer for PCIIRQ scan mechanism of
ICH5-R to support 16 PCIIRQs.
Revision 1.2

Table 19. Interrupt Definitions

Description
Intel order number C77866-003
Functional Architecture
57