Mixed Processor Steppings; Mixed Processor Models; Mixed Processor Families; Mixed Processor Cache Sizes - Intel SE7520AF2 Technical Product Specification

Intel® Server Board SE7520AF2 TPS
The BSP is responsible for executing the BIOS power-on self-test (POST) and preparing the
machine to boot the operating system. At boot time, the system is in virtual wire mode and the
BSP alone is programmed to accept local interrupts (INTR driven by programmable interrupt
controller (PIC) and non-maskable interrupt (NMI)).
As a part of the boot process, the BSP wakes each application processor (AP). When
awakened, an AP programs its Memory Type Range Registers (MTRRs) to be identical to those
of the BSP. All APs execute a halt instruction with their local interrupts disabled. If the BSP
determines that an AP exists that is a lower-featured processor or that has a lower value
returned by the CPUID function, the BSP switches to the lowest-featured processor in the
system.
5.3.2

Mixed Processor Steppings

For optimum system performance, only identical processors should be installed in a system.
Processor steppings can be mixed in a system provided that there is no more than a 1-stepping
difference in all processors installed. If the installed processors are more than 1-stepping apart,
an error (8080 through 8183) is logged in System Event Log (SEL) and an error (01298000
through 01298003) is reported to the Management Module. Acceptable mixed steppings are not
reported as errors.
Note: The error logging format for the Management Module and System Event Logging differ
from each other. See the Error Tables to determine which errors are logged in Management
Module and which errors are logged as part of System Error Logging.
5.3.3

Mixed Processor Models

Processor models cannot be mixed in a system. If this condition is detected an error is reported
and logged in SEL.
5.3.4

Mixed Processor Families

Processor families cannot be mixed in a system. If this condition is detected an error is reported
and logged in SEL.
5.3.5

Mixed Processor Cache Sizes

If the installed processors have mixed cache sizes, an error is reported and logged in the SEL.
The size of all cache levels must match between all installed processors.
5.3.6

Jumperless Processor Speed Settings

® TM
The Intel Xeon processor does not use jumpers or switches to set the processor frequency.
The BIOS reads the highest ratio register from all processors in the system. If all processors are
the same speed, the Actual Ratio register is programmed with the value read from the High
Ratio register. If all processors do not match, the highest common value between High and Low
Ratio is determined and programmed to all processors. If there is no value that works for all
installed processors, processors not capable of speeds supported by the BSP are disabled and
an error is displayed.
Revision 1.2
Intel order number C77866-003
System BIOS
107