Intel SE7520AF2 Technical Product Specification page 45

Intel® Server Board SE7520AF2 TPS Functional Architecture
Note: Event logging and annunciation is not supported for all RASUM events with the onboard
platform instrumentation. Event logging and annunciation for these advanced RASUM memory
features requires the presence of an Intel® Management Module – Professional Edition or
Advanced Edition.
3.3.6.1 DRAM ECC – Intel® x4 Single Device Data Correction (x4 SDDC)
The DRAM interface uses two different ECC algorithms. The first is a standard SEC/DED ECC
across a 64-bit data quantity. The second ECC method is a distributed, 144-bit S4EC-D4ED
mechanism, which provides x4 SDDC protection for DIMMS that utilize x4 devices. Bits from x4
parts are presented in an interleaved fashion such that each bit from a particular part is
represented in a different ECC word. DIMMs that use x8 devices, can use the same algorithm
but do not have x4 SDDC protection, since at most only four bits can be corrected with this
method. The algorithm does provide enhanced protection for the x8 parts over a standard SEC-
DED implementation. With two memory channels, either ECC method can be utilized with equal
performance, although single-channel mode only supports standard SEC/DED.
When memory mirroring is enabled, x4 SDDC ECC is supported in single channel mode when
the second channel has been disabled during a fail-down phase. The x4 SDDC ECC is not
supported during single-channel operation outside of DIMM mirroring fail-down as it does have
significant performance impacts in that environment.
3.3.6.2 Integrated Memory Scrub Engine
The Intel® E7520 MCH includes an integrated engine to walk the populated memory space
proactively seeking out soft errors in the memory subsystem. In the case of a single bit
correctable error, this hardware detects, logs, and corrects the data except when an incoming
write to the same memory address is detected.
For an uncorrectable error, the scrub engine logs the failure. Both types of errors may be
reported via multiple alternate mechanisms under configuration control. The scrub hardware
executes "demand scrub" writes when correctable errors are encountered during normal
operation (on demand reads, rather than scrub-initiated reads). This functionality provides
incremental protection against time-based deterioration of soft memory errors from correctable
to uncorrectable.
Using this method, a 16 GB system can be completely scrubbed in less than one day. The
effect of these scrub-writes does not cause any noticeable degradation to memory bandwidth,
although they cause a greater latency if a read that is delayed due to the scrub write cycle. This
is a very infrequent occurrence.
Note: An uncorrectable error encountered by the memory scrub engine is a "speculative error."
This designation is applied because no system agent has specifically requested use of the
corrupt data, and no real error condition exists in the system until that occurs. It is possible that
the error resides in an unmodified page of memory that will be dropped on a swap-back to disk.
If dropped the speculative error vanishes from the system, undetected and without adverse
consequences.
Revision 1.2 45
Intel order number C77866-003