I/O Sub-System; Pci Subsystem; Table 7. Pci Bus Segment Characteristics - Intel SE7520AF2 Technical Product Specification

Intel® Server Board SE7520AF2 TPS
Software toggles the SA[15] polarity via a configuration register bit setting. SA[15] was chosen
because it is the lowest system address bit that is always used to select the memory row
address across all DRAM densities and technologies supported by the Intel® E7520 MCH. The
toggling of the primary read location based on an address bit distributes request traffic across
the primary and mirror DIMMs, thereby distributing the thermal image of the workload across all
populated DIMM slots and reducing the chance of thermal-based memory traffic throttling.
In the mirrored operating state, the occurrence of correctable and uncorrectable ECC errors are
tracked and logged normally by the MCH and escalated to system interrupt events as specified
by the configuration register settings associated with errors on the memory subsystem.
Counters implementing the "leaky bucket" function for on-line DIMM sparing track the aggregate
count of single-bit and multiple-bit errors on a per DIMM basis.
The memory mirroring feature and DIMM sparing are exclusive of each other, only one may be
activated during initialization. The feature can be enabled in system BIOS setup. The selected
feature must remain enabled until the next power-cycle.
3.4

I/O Sub-System

The I/O sub-system is comprised of several components:
The MCH provides the PCI Express* interface to PCI Express* slots 3 and 4
The PXH provides the PCI-X interface for the dual gigabit Ethernet controller and PCI-X
slots 5 and 6
The IOP332 provides the PCI Express* to PCI bridge to interface the on-board SCSI
controller and PCI-X Slot 1
The ICH5-R provides the interface for the onboard video controller, Super IO chip, and
Management Sub-system
This section describes the function of each I/O interface and how they operate on the Intel®
Server Board SE7520AF2.
3.4.1

PCI Subsystem

The primary I/O interface for the Intel® Server Board SE7520AF2 is PCI, with six independent
PCI bus segments:
A PCI 32-bit 33 MHz bus segment (P32-A) enabled through the ICH5-R.
Two PCI-X 64-bit bus segments (P64-A 133MHz and P64-B 100MHz) enabled through
the PXH PCI Bridge.
Two PCI-X 64-bit bus segments (P64-A 133MHz and P64-B 133MHz) enabled through
the IOP332 I/O processor.
Two PCI Express* bus segments (PExp-B x8 and PExp-C x4) enabled through the MCH.
The table below lists the characteristics of the PCI bus segments.
PCI Bus Segment
Revision 1.2

Table 7. PCI Bus Segment Characteristics

Voltage Width Speed
Intel order number C77866-003
Functional Architecture
Type PCI I/O Card Slots
51