Intel SE7520AF2 Technical Product Specification page 193

Intel® Server Board SE7520AF2 TPS
and SERR# through NMI. Disabling NMI for PERR# and/or SERR# also disables logging of the
corresponding event. In the case of PERR#, the PCI bus master has the option to retry the
offending transaction, or to report it using SERR#. All other PCI-related errors are reported by
SERR#. All the PCI-to-PCI bridges are configured so that they generate SERR# on the primary
interface whenever there is SERR# on the secondary side, if SERR# is enabled through Setup.
The same is true for PERR#. The format of the data bytes is described above.
7.2.2.2 Processor Bus Error
If the chipset supports ECC on the processor bus, the BIOS will enables the error correction
and detection capabilities of the processors by setting appropriate bits in processor model
specific register (MSR) and appropriate bits inside the chipset.
In the case of irrecoverable errors on the host processor bus, proper execution of the
asynchronous error handler (usually SMI) cannot be guaranteed and the handler cannot be
relied upon to log such conditions. The handler will record the error to the system event log only
if the system has not experienced a catastrophic failure that compromises the integrity of the
handler.
7.2.2.3 Memory Bus Error
The hardware is programmed to generate an SMI on single-bit data errors in the memory array
if ECC memory is installed. The SMI handler records the error and the DIMM location to the
system event log. Double-bit errors in the memory array are mapped to SMI because the mBMC
cannot determine the location of the bad DIMM. The double-bit errors may have corrupted the
contents of SMRAM. The SMI handler will log the failing DIMM number to the mBMC if the
SMRAM contents are still valid. The ability to isolate the failure down to a single DIMM may not
be available on certain platforms, and/or during early POST.
7.2.2.4 System Limit Error
The BMC monitors system operational limits. It manages the A/D converter, defining voltage
and temperature limits as well as fan sensors and chassis intrusion. Any sensor values outside
of specified limits are fully handled by the BMC. The BIOS does not generate an SMI to the host
processor for these types of system events.
Refer to the platform's Server Management External Architecture Specification for details on
various sensors and how they are managed.
7.2.2.5 Processor Failure
The BIOS detects processor BIST failure and logs this event. The failed processor can be
identified by the first OEM data byte field in the log. For example, if processor 0 fails, the first
OEM data byte will be 0. The BIOS will depend upon BMC to log the watchdog timer reset
event.
If an operating system device driver is using the watchdog timer to detect software or hardware
failures and that timer expires, an Asynchronous Reset (ASR) is generated, which is equivalent
to a hard reset. The POST portion of the BIOS can query the BMC for watchdog reset event as
the system reboots, and logs this event in the SEL.
Revision 1.2
Intel order number C77866-003
Error Reporting and Handling
193