Intel SE7520AF2 Technical Product Specification page 226

Connectors, Headers and Jumpers
FMC Signal Name
SMB_I2C_3VSB_SDA
SMB_I2C_3VSB_SCL
PERIPH_I2C_3VSB_SDA
PERIPH_I2C_3VSB_SCL
MCH_I2C_3V_SDA
MCH_I2C_3V_SCL
LAN_I2C_3VSB_SDA
LAN_I2C_3VSB_SCL
HDD_FLT_LED_N
IMM_PS_PWR_ON_N
COOL_FLT_LED_N
IMM_CPU_VRD_EN
IMM_SCI_N
ICH_PWR_BTN_N
IMM_SPKR_N
FP_NMI_BTN_N
FP_SLP_BTN_N
FP_ID_BTN_N
SYS_PWR_GD
CPU2_SKTOCC_N
CLK_32K_RTC
226
FMC Pin
51 This bus should connect to the PCI slots, ICH, and mBMC (host I/F).
An isolated version of this bus (non-Standby) should connect to the
DIMMs, and clock buffer(s)
52 This bus should connect to the PCI slots, ICH, and mBMC (host I/F).
An isolated version of this bus (non-Standby) should connect to the
DIMMs, and clock buffer(s)
53 This bus should connect to the mBMC (Peripheral I/F), SIO, Heceta,
Front panel header. A level shifted version of this bus (5V Standby)
should connect to the Power Supply header
54 This bus should connect to the mBMC (Peripheral I/F), SIO, Heceta,
Front panel header. A level shifted version of this bus (5V Standby)
should connect to the Power Supply header
55 This bus should connect to the Northbridge and I/O bridge (MCH and
PXH respectively in the LH chipset). In a system that supports PCI
hot plug, this bus should also connect to the Power control devices if
possible (such as the MIC2591 for PCI Express* for example)
56 This bus should connect to the Northbridge and I/O bridge (MCH and
PXH respectively in the LH chipset). In a system that supports PCI
hot plug, this bus should also connect to the Power control devices if
possible (such as the MIC2591 for PCI Express* for example)
57 LAN usage
58 LAN usage
64 Drive Fault LED output driven when IMM detects a bad drive from the
Hot Swap controller on the Hot Swap disk Drive sub-system.
65 Power On Request to the system Power Supply
66 Cool Fault LED output driven when IMM detects a bad Fan if SSI
front panel is detect.
67 This signal is driven by the IMM to enable the CPU VRDs and allow
the VRD power good chain to complete. This signal can also be used
to keep the system in reset for an extended time, beyond what the
chipset RST_BTN_N can provide.
68 SCI event request. If ACPI EC is supported by IMM, this signal is
used for ACPI interrupts.
69 IMM pass through of Front panel power button to chipset
72 IMM uses this to create Beep Codes on the system audible alarm.
This signal is configured as an Open Drain buffer in the IMM and
must be pulled up to 3.3V Standby on the motherboard
73 NMI / Diagnostic interrupt from front panel. Actual NMI generated by
SMBUS command to mBMC
74 Front panel Sleep Button input, if used
75 Front panel ID button, will cause the ID light to toggle
76 Signal from the end of the baseboard VRD Power good chain. This
signal should be the last VRD power good indication generated on the
baseboard. Usually this would be the signal feeding the Chipset
Power OK input. Used by IMM in conjunction with RST_PWRGD_PS
to determine if all critical VRDs have successfully reached their
nominal value.
80 Indicates that a processor is in the application processor socket
81 This signal is used for "Synchronized clock with system RTC". IMM
can synchronize own RTC with system RTC. IPMI define
synchronized method. clock comes from the Chipset RTC function.
Intel order number C77866-003
Intel® Server Board SE7520AF2 TPS
Description
Revision 1.2