Table 25. Smm Space Transaction Handling - Intel SE7520AF2 Technical Product Specification

Intel® Server Board SE7520AF2 TPS
3.5.1.2.2 PCI Memory Space
Memory addresses below 4 GB range are mapped to the PCI bus. This region is divided into
three sections: High BIOS, APIC Configuration Space, and General-purpose PCI memory. The
General-purpose PCI memory area is typically used memory-mapped I/O to PCI devices. The
memory address space for each device is set using PCI configuration registers.
3.5.1.2.3 High BIOS
The top 1 MB of Extended memory under 4GB is reserved for the system BIOS, extended BIOS
for PCI devices, and A20 aliasing by the system BIOS. The "Nocona" and "Irwindale" processor
begins executing from the high BIOS region after reset.
3.5.1.2.4 I/O APIC Configuration Space
A 64 KB block located 20 MB below 4 GB (0FEC00000 to 0FEC0FFFFh) is reserved for the I/O
APIC configuration space.
The first I/O APIC is located at FEC00000h. The second I/O APIC is located at FEC80000h.
The third I/O APIC is located at FEC80100h.
3.5.1.2.5 Extended "Nocona" and "Irwindale" Processor Region (above 4GB)
The lntel(r) "Nocona" and "Irwindale" processor -based system can have up to 64 GB of
addressable memory. However, the Intel® E7520 chipset supports only 16 GB of addressable
memory. The BIOS uses the extended addressing mechanism to use the address ranges.
3.5.1.3 Memory Shadowing
The system BIOS and option ROM can be shadowed in main memory. This is done to allow
ROM code to execute more rapidly out of RAM. ROM is designated read-only during the copy
process while RAM at the same address is designated write-only. After copying, the RAM is
designated read-only. After the BIOS is shadowed, the attributes for that memory area are set to
read-only so that all writes are forwarded to the expansion bus.
3.5.1.4 System Management Mode Handling
The Intel® E7520 chipset supports System Management Mode (SMM) operation in one of three
modes. System Management RAM (SMRAM) provides code and data storage space for the
SMI_L handler code, and is made visible to the processor only on entry to SMM, or other
conditions, which can be configured using Intel® E7520 chipset. The MCH supports three SMM
options:
Compatible SMRAM (C_SMRAM)
High Segment (HSEG)
Top of memory Segment (TSEG)
Three abbreviations are used later in the table that describes SMM Space Transaction
Handling.
Revision 1.2

Table 25. SMM Space Transaction Handling

Intel order number C77866-003
Functional Architecture
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