Figure 17. Config_Addres Register - Intel SE7520AF2 Technical Product Specification

Intel® Server Board SE7520AF2 TPS
boot-strap processor (BSP) should perform PCI configuration space accesses. Precautions
should be taken to guarantee that only one processor performs system configuration.
Two Dword I/O registers in the Intel® E7520 chipset are used for the configuration space
register access: CONFIG_ADDRESS (I/O address 0CF8h), CONFIG_DATA (I/O address
0CFCh).
When CONFIG_ADDRESS is written to with a 32-bit value selecting the bus number, device on
the bus, and specific configuration register in the device, a subsequent read or write of
CONFIG_DATA initiates the data transfer to/from the selected configuration register. Byte
enables are valid during accesses to CONFIG_DATA; they determine whether the configuration
register is being accessed or not. Only full Dword reads and writes to CONFIG_ADDRESS are
recognized as a configuration access by the Intel® E7520 chipset. All other I/O accesses to
CONFIG_ADDRESS are treated as normal I/O transactions.
3.5.3.1 CONFIG_ADDRESS Register
CONFIG_ADDRESS is 32 bits wide and contains the field format shown in the following figure.
Bits [23::16] choose a specific bus in the system. Bits [15::11] choose a specific device on the
selected bus. Bits [10:8] choose a specific function in a multi-function device. Bit [8::2] select a
specific register in the configuration space of the selected device or function on the bus.
31 30
Reserved
Enable bit ('1' = enabled, '0' = disabled)
3.5.3.1.1 Bus Number
PCI configuration space protocol requires that all PCI buses in a system be assigned a bus
number. Bus numbers must be assigned in ascending order within hierarchical buses. Each PCI
bridge has registers containing its PCI Bus Number and subordinate PCI Bus Number, which
must be loaded by POST code. The Subordinate PCI Bus Number is the bus number of the last
hierarchical PCI bus under the current bridge. The PCI Bus Number and the Subordinate PCI
Bus Number are the same in the last hierarchical bridge.
3.5.3.1.2 Device Number and IDSEL Mapping
Each device under a PCI bridge has its IDSEL input connected to one bit out of the PCI bus
address/data signals AD[31::11] for the PCI bus. Each IDSEL-mapped AD bit acts as a chip
select for each device on PCI. The host bridge responds to a unique PCI device ID value, that
along with the bus number, cause the assertion of IDSEL for a particular device during
Revision 1.2
24 23
Bus Number
Figure 18. CONFIG_ADDRES Register
Intel order number C77866-003
16 15 11 10
Device Function
Functional Architecture
8 7
Register
1 0
0 0
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