System Management Headers; Intel Management Module Connector - Intel SE7520AF2 Technical Product Specification

Intel® Server Board SE7520AF2 TPS
FMC Signal Name
DVI_TX2M
DVI_CLK_TX1CP
DVI_TX2P
SIO_MS_DAT
SIO_KB_DAT
SIO_MS_CLK
SIO_KB_CLK
PS2_MS_DAT
PS2_KB_DAT
PS2_MS_CLK
PS2_KB_CLK
KM_INHIB_N
FML_SDA
FML_MCL_I2CSCL
FML_SINTEX
FML_MDA_I2CSDA
ICH_LCLK
USB_M
IMM_SYSIRQ
USB_P
ICH_LAD1
IMM_RSMRST_N
ICH_LFRAME_N
ICH_LAD0
ICH_LAD3
ICH_LPCPD_N
ICH_LAD2
IMM_LPCRST_N
DFP_CLK
DFP_DAT
IPMB_I2C_5VSB_SDA
IPMB_I2C_5VSB_SCL
Revision 1.2
FMC Pin
9 Red TMDS differential DVI output of graphics chip
10 TMDS differential DVI clock output of graphics chip
11 Red TMDS differential DVI output of graphics chip
14 KVM mouse data from SIO
15 KVM keyboard data from SIO
16 KVM mouse clock from SIO
17 KVM keyboard clock from SIO
18 KVM passthrough mouse data from PS2 connector
19 KVM passthrough keyboard data from PS2 connector
20 KVM passthrough mouse clock from PS2 connector
21 KVM passthrough keyboard clock from PS2 connector
22 KVM enable of baseboard Switch for mouse and keyboard
25 Fast Management Link Data In. This signal is driven by the FML
Slave, i.e. NIC controller
26 Fast Management Link Clock Out. This signal is driven by the FML
Master, i.e. IMM. When not configured as FML, this signal is used as
I2C clock.
27 Fast Management Link Slave Interrupt/Clock Extension. This signal is
driven by the FML Slave, and has a dual usage:
Used as an Alert signal for the slave to notify master that data is
ready to be read from slave
Used as a clock Extension (Stretching) for the slave to indicate to the
master to extend its low period of the clock
28 Fast Management Link Data Out. This signal is driven by the FML
Master. When not configured as FML, this signal is used as I2C data
31 LPC 33Mhz clock input
32 Reserved for future use as USB input. Baseboard can leave as NC
33 KCS interrupt signal from IMM Card.
34 Reserved for future use as USB input. Baseboard can leave as NC
35 LPC Address/data bus Bit 1
36 When this signal is asserted, the IMM is held in reset. This is a
Standby reset indication, and should be driven by a Standby monitor
device such as the Heceta7 or Dallas DS1815
37 LPC Cycle Framing
38 LPC Address/data bus Bit 0
39 LPC Address/data bus Bit 3
40 LPC Power down indication
41 LPC Address/data bus Bit 2
40 LPC bus reset. Must be properly buffered on motherboard to ensure
monotonicity
46 Serial clock signal for DFP EDID device. Must connect to DFP_CLK
pin on the graphics chip.
48 Serial data signal for DFP EDID device. Must connect to DFP_DAT
pin on the Graphics chip.
49 Connects to IPMB header
50 Connects to IPMB header
Intel order number C77866-003
Connectors, Headers and Jumpers
Description
225