Omron SYSMAC CJ - REFERENCE MANUAL 01-2008 Reference Manual page 1342

CS-series Instruction Execution Times and Number of Steps
Note
4-1-17 Subroutine Instructions
Instruction Mnemonic
SUBROUTINE CALL SBS
SUBROUTINE SBN
ENTRY
SUBROUTINE RET
RETURN
MACRO MCRO
GLOBAL SUBROU- GSBN
TINE CALL
GLOBAL SUBROU- GRET
TINE ENTRY
GLOBAL SUBROU- GSBS
TINE RETURN
4-1-18 Interrupt Control Instructions
Instruction Mnemonic
SET INTERRUPT MSKS
MASK
READ INTER- MSKR
RUPT MASK
CLEAR INTER- CLI
RUPT
DISABLE INTER- DI
RUPTS
ENABLE INTER- EI
RUPTS
4-1-19 Step Instructions
Instruction Mnemonic
STEP STEP
DEFINE
STEP SNXT
START
1. When a double-length operand is used, add 1 to the value shown in the
length column in the following table.
2. Supported only by CPU Units Ver. 2.0 or later.
Code Length
(steps)
(See note.)
091 2
092 2
093 1
099 4
751 2
752 1
750 2
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
Code Length
(steps)
(See note.)
690 3
692 3
691 3
693 1
694 1
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
Code Length
(steps)
(See note.)
008 2 17.4
11.8
009 2 6.6
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
ON execution time ( s)
CPU-6@H CPU-4@H
1.26 1.96
--- ---
0.86 1.60
23.3 23.3
--- ---
1.26 1.96
0.86 1.60
ON execution time ( s)
CPU-6@H CPU-4@H
25.6 38.4
11.9 11.9
27.4 41.3
15.0 16.8
19.5 21.8
ON execution time ( s)
CPU-6@H CPU-4@H CPU-6@
20.7 27.1
13.7 24.4
7.3 10.0
Section 4-1
Conditions
CPU-6@ CPU-4@
17.0 17.0 ---
--- --- ---
20.60 20.60 ---
23.3 23.3 ---
--- --- ---
--- --- ---
--- --- ---
Conditions
CPU-6@ CPU-4@
39.5 39.5 ---
11.9 11.9 ---
41.3 41.3 ---
16.8 16.8 ---
21.8 21.8 ---
Conditions
CPU-4@
27.1 Step control bit
ON
24.4 Step control bit
OFF
10.0 ---
1303