Usb Jtag - Xilinx SP605 User Manual

Chapter 1: SP605 Evaluation Board
Table 1-8: System ACE CF Connections (Cont'd)
Notes:
1. U17 System ACE CF controller 3.3V signals as named are wired to a set of TXB0108 3.3V-to-1.5V level
2. The System ACE CF clock is sourced from U29 32.000MHz oscillator.
References
See the System ACE CF product page for more information at
http://www.xilinx.com/support/documentation/system_ace_solutions.htm.
In addition, see the System ACE CompactFlash Solution Data Sheet.

6. USB JTAG

JTAG configuration is provided through onboard USB-to-JTAG configuration logic where
a computer host accesses the SP605 JTAG chain through a Type-A (computer host side) to
Type-Mini-B (SP605 side) USB cable. The JTAG chain of the board is illustrated in
Figure
initiated configuration takes priority over the mode pin settings.
X-Ref Target - Figure 1-6
22
U1 FPGA Pin Schematic Net Name
AA1 SYSACE_MPBRDY
W4
AA2
T6
T5
G17 SYSACE_CFGTDI
A21
E18
D20
N19 CLK_33MHZ_SYSACE(2)
shifters. The nets between the 1.5V side of the level shifters and the U1 FPGA have the same names
with _LS appended.
1-6. JTAG configuration is allowable at any time under any mode pin setting. JTAG
J4
Buffer
Figure 1-6: JTAG Chain Diagram
www.xilinx.com
(1)
SYSACE_MPCE
SYSACE_MPIRQ
SYSACE_MPOE
SYSACE_MPWE
FPGA_TCK
FPGA_TDI
FPGA_TMS
J19
FMC LPC System ACE CF
TDI TDO TSTTDI
TSTTDO
J2
U17
U17 XCCACETQ144I
Pin Number Pin Name
39 MPBRDY
42 MPCE
41 MPIRQ
77 MPOE
76 MPWE
81 CFGTDI
80 CFGTCK
82 CFGTDO
85 CFGTMS
93 CLK
[Ref 5]
3.3V 2.5V
FPGA
CFGTDO
TDI
CFGTDI
TDO
U1
UG526_06_092409
SP605 Hardware User Guide
UG526 (v1.1.1) February 1, 2010