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Register Description
2.10.36
MC_CHANNEL_0_ADDR_MATCH
MC_CHANNEL_1_ADDR_MATCH
MC_CHANNEL_2_ADDR_MATCH
This register specifies the intended address or address range where ECC errors will be
injected. It can be set to match memory address on a per channel basis. The address
fields can be masked in the Mask bits. Any mask bits set to 1 will always match. To
match all addresses, all of the mask bits can be set to 1. The
MC_CHANNEL_X_ECC_ERROR_INJECT register can be used to set the trigger for the
error injection.
Device:
Function: 0
Offset:
Access as a Qword
Bit
41
40
39
38
37
36
35:34
33:30
29:14
13:0
Datasheet
4, 5, 6
F0h
Reset
Type
Value
MASK_DIMM.
RW
0
1 = If set, ignore DIMM address during address comparison.
MASK_RANK.
RW
0
1 = If set, ignore RANK address during address comparison.
MASK_BANK.
RW
0
1 = If set, ignore BANK address during address comparison.
MASK_PAGE.
RW
0
If set, ignore PAGE address during address comparison.
MASK_COL.
RW
0
1 = If set ignore, COLUMN address during address comparison.
DIMM.
RW
0
DIMM address for 1 or 2DPC. For 3DPC, bits 36 and 35 represent the DIMM
address and bit 34 represent the RANK address.
RANK.
RW
0
Rank address for 1 or 2DPC. For 3DPC, bits 36 and 35 represent the DIMM
address and bit 34 represent the RANK address.
RW
0
BANK. Bank address.
RW
0
PAGE. Page address.
RW
0
COLUMN. Column address.
Description
81
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