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Table 2-16. Device 6, Function 0: Integrated Memory Controller Channel 2
Control Registers
DID
PCISTS
CCR
HDR
SID
MC_CHANNEL_2_DIMM_RESET_CMD
MC_CHANNEL_2_DIMM_INIT_CMD
MC_CHANNEL_2_DIMM_INIT_PARAMS
MC_CHANNEL_2_DIMM_INIT_STATUS
MC_CHANNEL_2_DDR3CMD
MC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_2_MRS_VALUE_0_1
MC_CHANNEL_2_MRS_VALUE_2
MC_CHANNEL_2_RANK_PRESENT
32
VID
00h
PCICMD
04h
RID
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
SVID
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
MC_CHANNEL_2_RANK_TIMING_A
MC_CHANNEL_2_RANK_TIMING_B
MC_CHANNEL_2_BANK_TIMING
MC_CHANNEL_2_REFRESH_TIMING
MC_CHANNEL_2_CKE_TIMING
MC_CHANNEL_2_ZQ_TIMING
MC_CHANNEL_2_RCOMP_PARAMS
MC_CHANNEL_2_ODT_PARAMS1
MC_CHANNEL_2_ODT_PARAMS2
MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD
MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RD
MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_WR
MC_CHANNEL_2_ODT_MATRIX_RANK_4_7_WR
MC_CHANNEL_2_WAQ_PARAMS
MC_CHANNEL_2_SCHEDULER_PARAMS
MC_CHANNEL_2_MAINTENANCE_OPS
MC_CHANNEL_2_TX_BG_SETTINGS
MC_CHANNEL_2_RX_BGF_SETTINGS
MC_CHANNEL_2_EW_BGF_SETTINGS
MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS
MC_CHANNEL_2_ROUND_TRIP_LATENCY
MC_CHANNEL_2_PAGETABLE_PARAMS1
MC_CHANNEL_2_PAGETABLE_PARAMS2
MC_TX_BG_CMD_DATA_RATIO_SETTING_CH2
MC_TX_BG_CMD_OFFSET_SETTINGS_CH2
MC_TX_BG_DATA_OFFSET_SETTINGS_CH2
MC_CHANNEL_2_ADDR_MATCH
MC_CHANNEL_2_ECC_ERROR_MASK
MC_CHANNEL_2_ECC_ERROR_INJECT
Register Description
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
CCh
D0h
D4h
D8h
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
Datasheet
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