Thread And Core Power State Descriptions; Power States; Coordination Of Thread Power States At The Core Level - Intel Core i7 Extreme Edition Datasheet

Figure 7-1.

Power States

C1
1. No transition to C0 is needed to service a snoop when in C1 or C1E.
2. Transitions back to C0 occur on an interrupt or on access to monitored address (if state was entered via MWAIT).
7.2.1

Thread and Core Power State Descriptions

Individual threads may request low power states. Core power states are automatically
resolved by the processor as shown in
Table 7-2.

Coordination of Thread Power States at the Core Level

Core State
Thread0
State
Notes:
1. If enabled, state will be C1E.
7.2.1.1 C0 State
This is the normal operating state in the processor.
7.2.1.2 C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1E) instruction. The processor thread will transition to the C0 state upon
occurrence of an interrupt or an access to the monitored address if the state was
entered via the MWAIT instruction. RESET# will cause the processor to initialize itself.
A System Management Interrupt (SMI) handler will return execution to either Normal
state or the C1 state. See the Intel
Manuals, Volume III: System Programmer's Guide for more information.
90
MWAIT C1,
HLT
2
2
MWAIT C1,
HLT (C1E
enabled)
1
1
C E 1
C0
C0
C0
1
C1
C0
C3
C0
C6 C0
C0
2
.
Table 7-2.
Thread1 State
1
C1 C3
C0 C0
1 1
C1 C1
1
C1 C3
1
C1 C3
®
64 and IA-32 Architecture Software Developer's
Features
MWAIT C6,
2
I/O C6
MWAIT C3,
I/O C3
C3 C6
,
.
C6
C0
1
C1
C3
C6
Datasheet