Table 37. Tpm Header/Port 80 Add-In-Card Header (J9A1); Table 38. Lpc Hot Docking (J9E5) - Intel ® Core i7 User Manual

4.6.2.11

Table 37. TPM Header/Port 80 Add-in-Card Header (J9A1)

4.6.2.12

Table 38. LPC Hot Docking (J9E5)

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TPM Header / Port 80 Add-in-Card Header
Pin
1 CLK_PCI_TPM
2 GND
3 LPC_FRAME#
4 N/C
5 BUF_PLT_RST#
6 +V5_R1_TPM
7 LPC_AD3
8 LPC_AD2
9 +V3.3S_R1_TPM
10 LPC_AD1
11 LPC_AD0
12 GND
13 SMB_CLK_S3
14 SMB_DATA_S3
15 +V3.3A_R1_TPM
16 INT_SERIRQ
17 GND
18 PM_CLKRUN#
19 PM_SUS_STAT#
20 TPM_DRQ#0
LPC Hot Docking
Pin
1
2
3
4
5
6
7
8
Signal
PCI Clock Loopback
Ground
LPC Frame
Reserved
Reset
5 volt supply
LPC Address/Data 3
LPC Address/Data 2
3.3 volt supply
LPC Address/Data 1
LPC Address/Data 0
Ground
SMB Clock
SMB Data
3.3 volt supply
Serial Interrupt Request
Ground
PCI Clock Run
Suspend Status
LPC DRQ
Signal
D_LAD_0
D_LAD_2
D_LAD_1
D_LAD_3
LPCD_PWRGD
LPCD_PWREN#
GND
LPCD_PCI_PME#
Definition
Dev Kit Manual