Table 12. Jumper Setting For Spi Programming - Intel ® Core i7 User Manual

events, CPU thermal monitoring/Fan control, GMCH thermal throttling support, LPC docking
support and power sequencing control.
The two PS/2 ports on motherboard are for legacy keyboard and mouse. The keyboard plugs
into the bottom jack and the mouse plugs into the top jack at J1A1. Scan matrix keyboards
can be supported via an optional connector at J9E3.
There is a LPC Slot (J8F2) and LPC Sideband connector (J9G2) on board to connect external
EC for validation purposes. On-board EC has to be disabled by shorting pin 1 and 2 of
connector J9F2 and an external EC has to take care of board power sequencing and thermal
management.
If the intention is just to read thermal information from the Chipset by external EC/Fan
controller, only Chipset SM-Bus signals (SML1_CLK and SML1_DATA) from the LPC sideband
connector can be used without connecting the EC on LPC slot.
For more information on the embedded controller please refer to Intel
®
(Intel ME) and Embedded Controller Interaction for Intel
Power Platform.
3.7.2.10
The Serial Peripheral Interface (SPI) on Intel
two compatible flash devices (U8C1 and U8D1), storing Unified BIOS Code. The SOIC-8
package (U8D2 and U8C2) would support 16 Mb SPI flashes, while the SOIC-16 (U8C1 and
U8D1) package will support 32Mb or higher SPI flash. One can opt to use SPI sockets, if they
wish to. Socket KOZ has been taken into account in the Layout. A Dediprog Header (J8E1) has
been provided for SPI Programming.
Note: Out of the SOIC-8 and SOIC-16 footprints supported on the board only one of these can be
used at a time and on the board. Footprint is arranged one over the other. By default, U8C1
(16Mb on CS#0) and U8D1 (16Mb on CS#1) will be stuffed.

Table 12. Jumper Setting for SPI Programming

3.7.2.11
The development kit system clocks are provided by the CK505 (EU6V1) clock synthesizer.
The BCLK frequency can be set using the BSEL Jumpers J6G1, J6F2, J6F3. Unlike previous
platforms it always needs to be 133MHz.
Dev Kit Manual
SPI
MODE
Normal
Operation
Programming
SPI0
Programming
SPI1
Clocks
®
Core™ i7 Processor Based Low-
®
QM57 Express Chipset can be used to support
J8D1 J8D3
1-X 1-X
3-X
1-2 1-2
3-X
1-2 1-X
2-3
®
Management Engine
J8D2
1-X
1-2
1-2
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