Sad - System Address Decoder Registers; Sad_Pam0123 - Intel BX80605I7870 - Core i7 2.93 GHz Processor Datasheet

Register Description
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Bit
4
3
2:0
2.6

SAD - System Address Decoder Registers

2.6.1

SAD_PAM0123

This register is for legacy device 0, function 0 at 90h-93h address space.
Device:
Function: 1
Offset:
Access as a Dword
Bit
29:28
Datasheet
0
0-1
06h
2
0-1, 4-5
06h
3
0-2, 4
06h
4-6
0-3
06h
Reset
Type
Value
Capability List (CLIST)
This bit is hardwired to 1 to indicate to the configuration software that this
device/function implements a list of new capabilities. A list of new capabilities is
accessed via registers CAPPTR at the configuration address offset 34h from the
RO TBD
start of the PCI configuration space header of this function. Register CAPPTR
contains the offset pointing to the start address with configuration space of this
device where the capability register resides. This bit must be set for a PCI
Express device or if the VSEC capability.
If no capability structures are implemented, this bit is hardwired to 0.
Interrupt Status
If this device generates an interrupt, then this read-only bit reflects the state of
the interrupt in the device/function. Only when the Interrupt Disable bit in the
command register is a 0 and this Interrupt Status bit is a 1, will the
RO 0
device's/function's INTx# signal be asserted. Setting the Interrupt Disable bit to
a 1 has no effect on the state of this bit.
If this device does not generate interrupts, then this bit is not implemented (RO
and reads returns 0).
RO 0 Reserved
0
40h
Reset
Type
Value
PAM3_HIENABLE. 0D4000h-0D7FFFh Attribute (HIENABLE).
This field controls the steering of read and write cycles that address the BIOS
area from 0D4000h to 0D7FFFh.
00 =DRAM Disabled: All accesses are directed to ESI.
RW 0
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
10 = Write Only: All writes are send to DRAM. Reads are serviced by ESI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Description
Description
41