Mc_Channel_0_Dimm_Init_Params; Mc_Channel_1_Dimm_Init_Params; Mc_Channel_2_Dimm_Init_Params - Intel BX80605I7870 - Core i7 2.93 GHz Processor Datasheet

Register Description
2.10.3

MC_CHANNEL_0_DIMM_INIT_PARAMS

MC_CHANNEL_1_DIMM_INIT_PARAMS

MC_CHANNEL_2_DIMM_INIT_PARAMS

Initialization sequence parameters are stored in this register. Each field is 2^n count.
Device:
Function: 0
Offset:
Access as a Dword
Bit
26
25
24
23
22
21:17
16
15
14:10
9:5
4:0
Datasheet
4, 5, 6
58h
Reset
Type
Value
DIS_3T.
When set, 3T mode will not be enabled as a part of the MRS write to the
RDIMM. The RC2 write to switch to 3T and back to 1T timing before and after an
RW 0
MRS write will not be done if the bit is set. This bit should be set if the RDIMM
supports auto MRS cycles where the dimm takes care of the 3T switching on
MRS writes.
DIS_AI.
When set, address inversion will not be disabled as a part of the MRS write to
RW 0
the RDIMM. The RC0 write to disable and enable address inversion will not be
done. This bit should be set if the RDIMM supports auto MRS cycles where the
dimm takes care of disabling address inversion for MRS writes.
THREE_DIMMS_PRESENT.
Set when channel contains three DIMMs. THREE_DIMMS_PRESENT=1 and
RW 0
QUAD_RANK_PRESENT=1 (or SINGLE_QUAD_RANK_PRESENT=1) are mutually
exclusive.
SINGLE_QUAD_RANK_PRESENT.
RW 0
Set when channel contains a single quad rank DIMM.
QUAD_RANK_PRESENT.
RW 0
Set when channel contains 1 or 2 quad rank DIMMs.
WRDQDQS_DELAY.
RW 15
Specifies the delay in DCLKs between reads and writes for WRDQDQS training.
WRLEVEL_DELAY.
Specifies the delay used between write CAS indications for write leveling
training.
RW 0
0 = 16 DCLKs.
1 = 32 DCLKs.
REGISTERED_DIMM.
RW 0
Set when channel contains registered DIMMs.
PHY_FSM_DELAY.
Global timer used for bounding the physical layer training. If the timer expires,
RW 0
the FSM will go to the next step and the counter will be reloaded with
PHY_FSM_DELAY value. Units are 2^n dclk.
BLOCK_CKE_DELAY.
RW 0
Delay in ns from when clocks and command are valid to the point CKE is
allowed to be asserted. Units are in 2^n uclk.
RESET_ON_TIME.
RW 0
Reset will be asserted for the time specified. Units are 2^n Uclk.
Description
61