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Register Description
2.8.4
MC_SMI_SPARE_CNTRL
System Management Interrupt and Spare control register.
Device:
Function: 0
Offset:
Access as a Dword
Bit
16
15
14:0
2.8.5
MC_RESET_CONTROL
DIMM Reset enabling controls.
Device:
Function: 0
Offset:
Access as a Dword
Bit
0
Datasheet
3
54h
Reset
Type
Value
INTERRUPT_SELECT_NMI
1 = Enable NMI signaling.
RW
0
0 = Disable NMI signaling.
If both NMI and SMI enable bits are set, then only SMI is sent.
INTERRUPT_SELECT_SMI
1 = Enable SMI signaling.
0 = Disable SMI signaling.
If both NMI and SMI enable bits are set, then only SMI is sent. This bit functions
the same way in Mirror and Independent Modes.
RW
0
The possible SMI events enabled by this bit are:
Any one of the error counters MC_COR_ECC_CNT_X meets the value of
SMI_ERROR_THRESHOLD field of this register.
MC_SSRSTATUS.CMPLT bit is set to 1.
MC_RAS_STATUS.REDUNDANCY_LOSS bit is set to 1.
SMI_ERROR_THRESHOLD
RW
0
Defines the error threshold to compare against the per-DIMM error counters
MC_COR_ECC_CNT_X, which are also 15 bits.
3
5Ch
Reset
Type
Value
BIOS_RESET_ENABLE
When set, MC takes over control of driving RESET to the DIMMs. This bit is set
WO
0
on S3 exit and cold boot to take over RESET driving responsibility from the
physical layer.
Description
Description
51
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