Mc_Channel_0_Tx_Bg_Settings; Mc_Channel_1_Tx_Bg_Settings; Mc_Channel_2_Tx_Bg_Settings; Mc_Channel_0_Rx_Bgf_Settings - Intel BX80605I7870 - Core i7 2.93 GHz Processor Datasheet

Register Description
2.10.26

MC_CHANNEL_0_TX_BG_SETTINGS

MC_CHANNEL_1_TX_BG_SETTINGS

MC_CHANNEL_2_TX_BG_SETTINGS

These are the parameters used to set the Start Scheduler for TX clock crossing. This is
used to send commands to the DIMMs.
The NATIVE RATIO is UCLK multiplier of BCLK = U
ALIEN RATION is DCLK multiplier of BCLK = D
PIPE DEPTH = 8 UCLK (design dependent variable)
MIN SEP DELAY = 670ps (design dependent variable, Internally this is logic delay of
FIFO + clock skew between U and D)
TOTAL EFFECTIVE DELAY = PIPE DEPTH * UCLK PERIOD in ps + MIN SEP DELAY
DELAY FRACTION = (TOTAL EFFECTIVE DELAY * D) / (UCLK PERIOD in ps * G.C.D(U,D)
Determine OFFSET MULTIPLE using the equation
FLOOR ((OFFSET MULTIPLE +1) / G.C.D (U,D)) > DELAY FRACTION
OFFSET VALUE = MOD (OFFSET MULTIPLE, U) <= Final answer for OFFSET MULTIPLE
Device:
Function: 0
Offset:
Access as a Dword
Bit
23:16
15:8
7:0
2.10.27

MC_CHANNEL_0_RX_BGF_SETTINGS

MC_CHANNEL_1_RX_BGF_SETTINGS

MC_CHANNEL_2_RX_BGF_SETTINGS

These are the parameters used to set the Rx clock crossing BGF.
Device:
Function: 0
Offset:
Access as a Dword
Bit
26:24
23:16
15:8
7:0
Datasheet
4, 5, 6
C0h
Reset
Type
Value
RW 2
OFFSET. TX offset setting.
RW 1 ALIENRATIO. Dclk ratio to BCLK. TX Alien Ratio setting.
RW 4 NATIVERATIO. Uclk ratio to BCLK. TX Native Ratio setting.
4, 5, 6
C8h
Reset
Type
Value
PTRSEP.
RX FIFO pointer separation settings. THIS FIELD IS NOT USED BY HARDWARE.
RW 2
RX Pointer separation can be modified via the round trip setting (larger value
causes a larger pointer separation).
RW 0 OFFSET. RX offset setting.
RW 1 ALIENRATIO. Qclk to BCLK ratio. RX Alien Ratio setting.
RW 2 NATIVERATIO. Uclk to BCLK ratio. RX Native Ratio setting.
Description
Description
77