Mc_Smi_Spare_Dimm_Error_Status - Intel BX80605I7870 - Core i7 2.93 GHz Processor Datasheet

2.8.3

MC_SMI_SPARE_DIMM_ERROR_STATUS

SMI sparing DIMM error threshold overflow status register. This bit is set when the per-
DIMM error counter exceeds the specified threshold. The bit is reset by BIOS.
Device:
Function: 0
Offset:
Access as a Dword
Bit
13:12
11:0
50
3
50h
Reset
Type
Value
0 REDUNDANCY_LOSS_FAILING_DIMM
RW0C
The ID for the failing DIMM when redundancy is lost.
0 DIMM_ERROR_OVERFLOW_STATUS
This 12-bit field is the per dimm error overflow status bits. The organization is
as follows:
If there are three or more DIMMS on the channel:
Bit 0 = DIMM 0 Channel 0
Bit 1 = DIMM 1 Channel 0
Bit 2 = DIMM 2 Channel 0
Bit 3 = DIMM 3 Channel 0
Bit 4 = DIMM 0 Channel 1
Bit 5 = DIMM 1 Channel 1
Bit 6 = DIMM 2 Channel 1
Bit 7 = DIMM 3 Channel 1
Bit 8 = DIMM 0 Channel 2
Bit 9 = DIMM 1 Channel 2
Bit 10 = DIMM 2 Channel 2
RW0C
Bit 11 = DIMM 3 Channel 2
If there are one or two DIMMS on the channel:
Bit 0 = DIMM 0, Ranks 0 and 1, Channel 0
Bit 1 = DIMM 0, Ranks 2 and 3, Channel 0
Bit 2 = DIMM 1, Ranks 0 and 1, Channel 0
Bit 3 = DIMM 1, Ranks 2 and 3, Channel 0
Bit 4 = DIMM 0, Ranks 0 and 1, Channel 1
Bit 5 = DIMM 0, Ranks 2 and 3, Channel 1
Bit 6 = DIMM 1, Ranks 0 and 1, Channel 1
Bit 7 = DIMM 1, Ranks 2 and 3, Channel 1
Bit 8 = DIMM 0, Ranks 0 and 1, Channel 2
Bit 9 = DIMM 0, Ranks 2 and 3, Channel 2
Bit 10 = DIMM 1, Ranks 0 and 1, Channel 2
Bit 11 = DIMM 1, Ranks 2 and 3, Channel 2
Register Description
Description
Datasheet