Mc_Channel_0_Dimm_Init_Status; Mc_Channel_1_Dimm_Init_Status; Mc_Channel_2_Dimm_Init_Status - Intel BX80605I7870 - Core i7 2.93 GHz Processor Datasheet

2.10.4

MC_CHANNEL_0_DIMM_INIT_STATUS

MC_CHANNEL_1_DIMM_INIT_STATUS

MC_CHANNEL_2_DIMM_INIT_STATUS

The initialization state is stored in this register. This register is cleared on a new
training command.
Device:
Function: 0
Offset:
Access as a Dword
Bit
9
8
7
6
5
4
3
2:0
62
4, 5, 6
5Ch
Reset
Type
Value
RCOMP_CMPLT.
RO 0
When set, indicates that RCOMP command has complete. This bit is cleared by
hardware on command issuance and set once the command is complete.
INIT_CMPLT.
RO 0
This bit is cleared when a new training command is issued. It is set once the
sequence is complete regardless of whether all steps passed or not.
ZQCL_CMPLT.
RO 0
When set, indicates that ZQCL command has completed. This bit is cleared by
hardware on command issuance and set once the command is complete.
WR_DQ_DQS_PASS.
RO 0
Set after a training command when the Write DQ-DQS training step passes.
The bit is cleared by hardware when a new training command is sent.
WR_LEVEL_PASS.
RO 0
Set after a training command when the write leveling training step passes. The
bit is cleared by hardware when a new training command is sent.
RD_RCVEN_PASS.
RO 0
Set after a training command when the Read Receive Enable training step
passes. The bit is cleared by hardware when a new training command is sent.
RD_DQ_DQS_PASS.
RO 0
Set after a training command when the Read DQ-DQS training step passes. The
bit is cleared by hardware when a new training command is sent.
PHYFSMSTATE.
The current state of the top level training FSM.
000 = IDLE
RO 0
001 = RD DQ-DQS
010 = RcvEn Bitlock
011 = Write Level
100 = WR DQ-DQS
Register Description
Description
Datasheet