Mc_Channel_0_Odt_Params2; Mc_Channel_1_Odt_Params2; Mc_Channel_2_Odt_Params2; Mc_Channel_0_Odt_Matrix_Rank_0_3_Rd Mc_Channel_1_Odt_Matrix_Rank_0_3_Rd Mc_Channel_2_Odt_Matrix_Rank_0_3_Rd - Intel BX80605I7870 - Core i7 2.93 GHz Processor Datasheet

Register Description
2.10.18

MC_CHANNEL_0_ODT_PARAMS2

MC_CHANNEL_1_ODT_PARAMS2

MC_CHANNEL_2_ODT_PARAMS2

This register contains parameters that specify Forcing ODT on Specific ranks. This
register is used in debug only and not during normal operation.
Device:
Function: 0
Offset:
Access as a Dword
Bit
9
8
7
6
5
4
3
2
1
0
2.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD
MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD
MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD
This register contains the ODT activation matrix for RANKS 0 to 3 for Reads.
Device:
Function: 0
Offset:
Access as a Dword
Bit
31:24
23:16
15:8
7:0
Datasheet
4, 5, 6
A0h
Reset
Type
Value
RW 0 MCODT_Writes. Drive MC ODT on reads and writes.
RW 0 FORCE_MCODT. Force MC ODT to always be asserted.
RW 0 FORCE_ODT7. Force ODT for Rank7 to always be asserted.
RW 0 FORCE_ODT6. Force ODT for Rank6 to always be asserted.
RW 0 FORCE_ODT5. Force ODT for Rank5 to always be asserted.
RW 0 FORCE_ODT4. Force ODT for Rank4 to always be asserted.
RW 0 FORCE_ODT3. Force ODT for Rank3 to always be asserted.
RW 0 FORCE_ODT2. Force ODT for Rank2 to always be asserted.
RW 0 FORCE_ODT1. Force ODT for Rank1 to always be asserted.
RW 0 FORCE_ODT0. Force ODT for Rank0 to always be asserted.
4, 5, 6
A4h
Reset
Type
Value
RW 1 ODT_RD3. Bit patterns driven out onto ODT pins when Rank3 is read.
RW 1 ODT_RD2. Bit patterns driven out onto ODT pins when Rank2 is read.
RW 4 ODT_RD1. Bit patterns driven out onto ODT pins when Rank1 is read.
RW 4 ODT_RD0. Bit patterns driven out onto ODT pins when Rank0 is read.
Description
Description
73