Pll Synthesizer Circuit; Rx Board Self-Test Detection Circuit - Furuno FS-1575 Service Manual

4. PLL Synthesizer circuit

A circuit that outputs 1st Lo frequency consists of PLL and DDS circuits. An 18 MHz
reference frequency from the TX board is inputted to "U9" PLL IC.
The PLL IC converts the 18 MHz reference frequency to a 6 MHz reference frequency
to output a 396 MHz frequency. However, in order to avoid spurious reception at a
specific reception frequency, it may output a 384 MHz frequency.
A 396 MHz frequency outputted from the PLL circuit is inputted in the DDS circuit, and
the 1st Lo frequency is outputted from the DDS circuit according to data on received
frequencies up to 10 Hz digits.
The 1st Lo frequency is injected in the "U7" 1st mixer to convert a received signal to
the 1st IF signal of F+54.964 MHz.
The 2nd Lo frequency is 54 MHz obtained by trebling an 18 MHz frequency from the
TX board.
The 2nd Lo frequency is injected in the "U6" 2nd mixer to convert a received signal to
the 2nd IF signal of 36 kHz.

5. RX board self-test detection circuit

When conducting a self-test, the test results will be checked with the UN-LOCK and
RX HW VER signals.
1) UN-LOCK
PLL circuit "lock or unlock" detection signal. When it detects that the PLL circuit
is unlocked, transmission will be stopped and an error message saying
"WARNING: TX PLL UNLOCK!" will be outputted.
2) RX HW VER
RX board hardware information. This information will be displayed when
selecting [MENU] -> 9.SERVICE -> 5.TEST -> 1.VERSION.
CONFIDENTIAL (internal use only)
This confidential document is used only by FURUNO authorized persons.
It is strictly prohibited to reproduce the document in whole or in part without prior written permission of FURUNO.
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7.3 Receiver Circuit