F Circuit Diagram (Okifax4550); Circuit Diagram (1/13) - Oki OKIFAX4550 Maintenance Manual

3.

46F Circuit Diagram (OKIFAX4550)

3.1 46F Circuit Diagram (1/13)
1. Block diagram
46F-PCB circuit diagram (1/13) shown the consists of an input/output gate array IC2 (IOGA4),
crystal oscillator circuit and reset signal generator.
Figure A.6 shown the block diagram of IC2 (IOGA4) and the peripheral circuits.
2. Function
1) IOGA4 is newly developed LSI for scanning, printing control and provided with a built-in
CPU.
- IOGA4 contains the following functions:
• Scanned data DMA control
• Strobe signals control for LED head
• Smoothing control for printing data
• Interface of the peripheral LSI
- CPU
CPU controls the following functions in addition to the basic processor.
• DMA (Direct Memory Access) control
• Interrupt procedure control
• A/D converter
• Bus state control
• Programmable pattern control
• 16 bit integrated timer pulse unit (ITU)
• Timing pattern control (TPC)
• Serial communication interface (SCT)
2) Crystal oscillator circuit
X1 is 20MHz crystal oscillator. The output wave is fed to the IOGA4 (CPU) through pin 14
and 15. CLK (20MHz) signal output from pin 94 is used as the system clock.
Address Bus
Initial Reset Circuit
+5V
Data/Address Bus
Various Sensor
Data/Address Bus
Data/Address Bus
41309401TH Rev.4
1/4
(CPU: SH7034)
IC1
POWRDY
X1
XTAL
EXTAL
20 MHz
2/4
Printer control
OST-EX
Buffer 640 bytes
Decoding
(RLE,TIFF,ACC32)
200-300 converter
smoothing
3/4
Peripheral control
1284 control
CS generation
I/O port
DMA 2ch
4/4
High-voltage
Controller
Figure A.6 Related Signals of IOGA4
Data/Address bus
CLK CLK
20 MHz
LED head
300 dpi
M D-motor
Clutch
Bi-Centro
I/F
OPE unit
Speaker
High-voltage
Power Supply
310 /