Commodore 128 Programmer's Reference Manual page 645

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C128 HARDWARE SPECIFICATIONS 635
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THE EXPANSION BUS
The C128 Expansion Bus is compatible with the C64 Expansion Bus, while at the same
time allowing extended capabilities in C128 mode.
CARTRIDGE ADDITION
The C128 can use larger and more sophisticated cartridges than the C64. One of the
main reasons for this is the new banking scheme used in the C128 for external
cartridges. The C64 uses two hardware control lines, /EXROM and /GAME, to control
banking out of internal facilities and banking in of cartridge facilities. The C128 uses a
software polling method, where upon power-up it polls the cartridge, according to a
defined protocol, to determine if such a cartridge exists, and if so, what its software
priority is. Since the C128 is always free to bank between cartridges and built-in ROM,
an external application can take advantage of internal routines and naturally become an
extended part of the C128, as opposed to becoming a replacement application. See
Chapter 13 for information on the Auto Start Cartridge ROM sequence.
The elimination of /EXROM and /GAME as hardware control lines for cartridge
identification (in C128 mode) has freed up both of these lines for extended functioning.
Both of the lines appear as bits in the MMU Mode Configuration Register, and are both
input and output ports. Neither has a dedicated function other than general cartridge
function expansion, and lend themselves to act as latched banking lines or input sense
lines. Of course, neither can be asserted on C128 power-up or C64 mode will automati
cally be set.
DMA CAPABILITY
The C128 expansion bus supports DMAs in a fashion similar to that of the C64. A C64
DMA is achieved by pulling the /DMA pin on the expansion bus low. Immediately after
this happens, the RDY and AEC lines of the processor are brought low. This can neatly
shut down the processor, but it can also cause problems, depending on what the
processor is doing at the time. The RDY input of an 8502 series processor, when brought
low, will halt the processor of the next <I>1 cycle, leaving the processor's address lines
reflecting the current address being fetched. However, if the processor is in a write cycle
when RDY is brought low, it will ignore RDY until the next read cycle. Thus, in the
C64, a /DMA input occurring during a write cycle will tri-state the processor's address
and data bus, but not stop it until up to three cycles later when the next read cycle
occurs. The write cycles following the /DMA input do not actually write, causing
memory corruption and often processor fatality when the /DMA line is released. Any
/DMA input during <&2 is a potentially fatal DMA.
If a proper /DMA is asserted, the C64 tri-states and shuts down, allowing the
DMA source complete access to the processor bus. Such a DMA source must monitor
the 02 and BA outputs, as it must tri-state when the VIC is on the bus, and it must
completely DMA when a VIC DMA is called for. The VIC chip always has the highest