Commodore 128 Programmer's Reference Manual page 418

408 COMMODORE 128
configuration on the stack, brings the system configuration (ROM's, I/O, RAMO) U
into context, and executes an indirect jump through the RAM vector located at
$318. The system NMI handler clears the ICR register of CIA-2, from which it w
determines the source of the interrupt. If it is from timer A, control passes to the j I
RS-232 transceiver. If not, the RESTORE key is assumed, and for safety,
the CBM convention of requiring the STOP key to be simultaneously de
pressed is checked. If the STOP key is depressed, all system indirect vectors are
restored, IOINIT and CINT are called, and the SYSTEM_VECTOR (do not <->
confuse with the SYSTEM vector!) is taken. Control is returned upon restoration of
the registers and memory configuration. NMFs may be disabled by causing an initial ) I
NMI from timer A, but never reading the ICR to clear it, thus keeping the NMI JJ
signal grounded.
Application software can intercept an NMI event by modifying either of the , ,
two RAM vectors mentioned above. The NMI indirect vector at $318 in common j j
RAM will pass control whenever an NMI occurs. The SYSTEM_VECTOR, located ^
at $A00 in RAMO, will pass control after STOP/RESTORE is detected and handled.
For example, suppose a situation similar to the one illustrated previously for j
the SYSTEM vector occurs. To return control to the Monitor whenever STOP/ U
RESTORE is detected, enter:
a. >A00 00 BO :aim SYSTEM-VECTOR to Monitor j j
Similarly, to perform an action anytime an NMI occurs (e.g., RESTORE
alone), use the NMI indirect. For example, increment the VIC border color when
ever you press RESTORE (or cause any other NMI). Enter:
a. >318 00 13 :aim indirect to $1300
b. A 1300 INC $D020 xhange border color ^
JMP$FF33 :return from interrupt \ j
Lj
3. $FFFC RESET ;processor RESET vector j ,
The processor RESET vector is activated whenever the system RESET signal is lu
low. It is low at power-up, and is pulled low by pressing the RESET button. This
signal effects not only the processor but most of the I/O devices found in the \ j
system. In fact, RESET is the one processor control signal that is shared between jj
the two processors (8502 and Z80) of the C128. The Z80 gains initial (default)
control of the system while the 8502 is held in a waiting state. When the 8502
finally starts after a reset, the Kernal initialization routine START always receives j {
control and immediately performs the following actions: ^
1. Brings the system map into context.
2. Disables IRQ's. j |
3. Resets the processor stack pointer. ^
4. Clears decimal mode.
5. Initializes the MMU. \ I
6. INSTALLS the Kernal RAM code. M