Commodore 128 Programmer's Reference Manual page 605

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C128 HARDWARE SPECIFICATIONS 595
THE 8563
H VIDEO CONTROLLER
I I ■—-~ —
The 8563 is a HMOSII technology custom 80-column, color video display controller.
1} The 8563 supplies all necessary signals to interface directly to 16K of DRAM, including
1 * refresh, and generated RGBI for use with an external RGBI monitor. For more informa
tion on the 8563 video controller, see Chapter 10, Programming the 80-Column (8563) Chip.
! GENERAL DESCRIPTION
The 8563 is a text display chip designed to implement an 80-column display system with
P| a minimum of parts and cost. The chip contains the high-speed pixel frequency logic
/ i necessary for 80-column RGBI video. It can drive loads directly, though some buffering
is desirable in most real-world applications. The chip can address up to 64K of DRAM
py for character font, character pointer, and attribute information. The chip provides RAS,
! i CAS, write enable, address, data and refresh for its subordinate DRAMs. A program
mable bit selects either two 4416 DRAMs (16K total) or eight 4164 DRAMs (64K total)
for the display RAM. The C128 system uses the 4416 DRAMs.
! | EXTERNAL REGISTERS
The 8563, which sits at $D600 in the C128, appears to the user as a device consisting of
Ronly two registers. These two registers are indirect registers that must be programmed to
access the internal set of thirty-seven programming registers. The first register, located
at $D600, is called the Address Register. Bit 7 of $D600 is the Update Ready Status Bit.
When written to, the five least significant bits convey the address of an internal register
P| to access in some way. On a read of this register, a status byte is returned. Bit 7 of this
; i register is low while display memory is being updated, and goes high when ready for the
next operation. The sixth bit will return low for an invalid light pen register condition and
n high for a valid light pen address. The final register indicates with a low that the scan is
| j not in vertical blanking, and with a high that it is in vertical blanking.
The other register is the Data Register. It can be read from and written to. Its
purpose is to write data to the internal register selected by the address register. All
j i internal registers can be read from and written to through this register, though not all of
' ^ them are a full 8 bits wide.
H INTERNAL REGISTERS
| j There are thirty-seven internal registers in the 8563, used for a variety of operations.
They fall into two basic groups: setup registers and display registers. Setup registers are
used to define internal counts for proper video display. By varying these registers, the
H user can configure the 8563 for NTSC, PAL or other video standards.
f I The display registers are used to define and manipulate characters on the screen.
Once a character set has been downloaded to this chip, it is possible to display
80-column text in 4-bit digital color. There are also block movement commands that
remove the time overhead needed to load large amounts of data to the chip through the
two levels of indirection. Figure 16-11 is a display of the 8563 internal register map.