Commodore 128 Programmer's Reference Manual page 571

C128 HARDWARE SPECIFICATIONS 561
j !
] chip by driving the multiplexed adcfress buses. It directly drives system ROM 4 address
line 12 to allow the Z80 ROM relocation. Finally, this bus becomes address lines 8
!"j through 15 of the C64 compatible expansion port.
I ! During a VIC cycle or a DMA, the MMU pulls TA12-TA15 high, while TAg-TAj,
are tri-stated. This allows the VIC chip to drive TAs-TAn as VIC addresses VAg-VAn.
p-» During an external DMA cycle, the TA lines of the MMU are tri-stated, and the TA
j j bus, presumably driven by the DMA source, in turn drives the processor address bus
from A8 to AJ5. Thus allows the DMA source to access any peripheral chip except the
^ MMU. The action of the VIC during a VIC cycle is described below.
I THE MULTIPLEXED ADDRESS BUS
This section describes two related address buses, the Multiplexed Address Bus and the
H VIC Multiplexed Address Bus, known respectively as MA(r-MA7 and VMA0-VMA7.
/ ; The VIC multiplexed address bus is created during AEC high by multiplexing the
high-order translated address bus (TA8-TA15) with the low-order processor address bus
n (Aor-A7), controlled via the MUX signal. This bus, driven by a hardware multiplexer
! j through series resistors, is called the Multiplexed Address Bus. The VIC multiplexed
' address bus is used for processor access of the VIC chip registers. It is also used for VIC
access of system RAM.
p During a VIC cycle (AEC low), the VIC chip address lines will be asserted. There
! I is no completely separate address bus for the VIC addresses, so it shares the VMA0-VMA7
and address lines that are tri-stated during AEC high. Most of the VIC addresses come
(—I out of the VIC chip already multiplexed, but two of them, VA6 and VA7, do not supply
j j column information, as the VIC chip supplies only 14 bits of addressing. The higher-
order address bits VA14 and VA15 come from CIA-2, as in the C64. This means the VIC
supplies complete VMA0-VMA7 for a VIC DRAM access or DRAM refresh. The
I j TAg-TAn supplied by VIC are used in conjunction with another addressing bus for
' 1 nonmultiplexed VIC cycle addresses, such as character ROM and color RAM accesses.
n THE SHARED ADDRESS BUS
\ \ The Shared Address Bus is a nonmultiplexed address bus used by both the processor
and the VIC chip to communicate with common resources, namely the character ROM
^ and color RAM (and the 8563 system RAM indirectly). During AEC high, the shared
j i address bus, designated Sao-SA7, is driven by A0-A7, the lower-order processor
^ address bits. The higher-order bits needed are supplied by the translated address bus,
which is also a shared address bus. Thus, the processor is able to access both shared
H items.
) i During AEC low, the VIC addresses VAq-VA7 (VMA0-VMA7) must come onto
the shared address bus. Since VAo-VA8 are actually multiplexed, the row address only
pi must be sent to the shared address bus. Thus, the multiplexed VIC addresses are
j ! transparently gated when either /RAS or MUX are high, but latched and held afterward
1 so that when combined with the column address, the full address is presented. The high-
order address bits here are supplied by the shared translated address bus. Note that the
P| shared address bus provides the lower 8 bits of the expansion port address, allowing VIC
1 access to cartridges and some additional drive capability by way of the TTL chips used to