Commodore 128 Programmer's Reference Manual page 337

PROGRAMMING THE 80-COLUMN (8563) CHIP 327
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f ! R 10(4-0) and Rl 1(4-0). These registers allow the 8563 to be programmed for a
reverse-video "block" cursor, or for an "underline" cursor. The location of the cursor
p can be changed by changing the contents of registers R14 and R15.
RI6, RI7 LIGHT PEN VERTICAL, HORIZONTAL
p The 8563 supports a light pen function. When the LPEN input pin transitions from a low
( to high, the 8563 latches the current vertical and horizontal character counts in the two
f light pen registers. The vertical count is latched in R16. LPEN transitions that occur
during the row at the top of the frame will latch a 1 in R16. Transitions on subsequent
"I rows will latch 2, 3, etc. The horizontal count is latched in R17. LPEN transitions that
» occur during the leftmost character column will latch an 8. Transitions on subsequent
columns will latch 9, 10, etc. The condition of the light pen registers is latched in bit 6 of
n the status register. If 0, the light pen registers have not been latched and contain invalid
I j data. If 1, the registers contain valid latched data. A CPU read of R16 or R17 resets
the Status Register bit.
P READ AND WRITE DISPLAY
8563 RAM MEMORY
H RI8, RI9 UPDATE LOCATION
1 R3I CPU DATA
The CPU communicates to the 8563 RAM memory via address and data registers in
P the 8563. For the CPU to read a memory location, it must place that address in registers
! ! R18 (most significant byte) and R19 (least significant). The 8563 responds by executing
a read of that memory location and placing that data into R31, which the CPU may then
[-} read. During the time that the "read" is pending and data is not yet valid in R31, the
I i Update Ready bit of the status register (bit 7) will be 0. Upon completion of the read
' cycle, data will be valid in R31 and the bit will be 1. When the CPU reads the data in
R31, the 8563 increments the address in R18/R19 and performs a read of that address.
(j This allows the CPU to read successive memory locations without repeatedly changing
' ' the addresses in R18/R19.
For the CPU to write data to a memory location, the address must be written to
P R18/R19 as in a "read" described above. Following the automatic read and after the
I ! Update Ready bit is a 1, the CPU should write the desired data to R31. The 8563 then
writes the data to 8563 Memory at the address defined by R18/R19, increments the
(—> address in R18/R19, reads the data from the incremented memory location and places it
| j in R31. The 8563 then sets the Update Ready bit to a 1. At all times, if the Update
Ready bit is a 0, then CPU access to 8563 memory is pending. Additional access of R18,
R19 or R31 should be avoided until the Update Ready bit is a 1.
R20, R2I ATTRIBUTE START ADDRESS (HIGH, LOW)
The address for the attribute of the first (top-left) character of the frame is defined in
R20 and R21. The most significant 8 bits is in R20, the least significant in R21. These
set the complete 16-bit address for that first attribute. The address of attributes of