Commodore 128 Programmer's Reference Manual page 165

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* MACHINE LANGUAGE ON THE COMMODORE 128 155
' I BCC—(Branch on Carry Clear) Branch if the Carry flag in the status register equals 0.
BCS—(Branch on Carry Set) Branch if the Carry flag in the status register equals 1.
pj BEQ—(Branch on result EQual zero) Branch if the zero flag in the status register equals 1.
> | BMI—(Branch on result Minus) Branch if the negative flag in the status register equals 1.
BNE—(Branch on result Not Equal to zero) Branch if the zero flag in the status register
fmmt equals 0.
I ! BPL—(Branch on result PLus) Branch if the negative flag in the status register equals 0.
' ! BVC—(Branch on oVerflow Clear) Branch if the overflow flag in the status register
equals 0.
*-; BVS—(Branch on oVerflow Set) Branch if the overflow flag in the status register
| I equals 1.
As you can see, all branching instructions depend on the value of a flag in the
J"? status register.
/ ! Here are some branching examples.
READY.
I) MONITOR
1 j PC SR AC XR YR SP
; FB000 00 00 00 00 F8
01828 E6 FA INC $FA
0182A A5 FA LDA $FA
0182C DO 02 BNE $1830
0182E E6 FB INC $FB
01830 C8 INY
This program segment keeps track of the low and high pointers in $FA and $FB
respectively. The first instruction (INC $FA) increments the low byte address pointer.
Next, the contents of $FA is loaded into the accumulator. The branch instruction (BNE
$1830) evaluates the value of the accumulator. If the value is not equal to zero, the
branch is taken to the instruction located at address $1830 (INY). In this case the high
byte pointer is not yet ready to be incremented, so the INC $FB instruction is skipped. If
the value in the accumulator is equal to zero, the branch is skipped and the high byte
address pointer is incremented.
This is an example of the BPL (Branch on Result Plus) instruction.
READY.
MONITOR
PC SR AC XR YR SP
; FB000 00 00 00 00 F8
. 01858 8E 00 D6 STX $D600
. 0185B 2C 00 D6 BIT $D600
. 0185E 10 FB BPL $185B
. 01860 8D 01 D6 STA $D601
This example is a routine that checks the update ready status bit for the 8563
address register, and ensures that data is valid before writing a value to an 8563 register.
The first instruction stores the contents of the X register, which was previously loaded