Commodore 128 Programmer's Reference Manual page 576

566 COMMODORE 128
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CI28 RAM MEMORY ORGANIZATION u
As shown in Figure 16-2, the RAM present in the system is actually composed of two
banks of 64K by 8 bytes of DRAM. The RAM is accessed by selecting one of the two 64K j j
banks, the maximum address range of the 8502 and Z80, according to the RAM banking lJ
rules set in the RAM configuration register of the MMU. This area shown as RAM
represents what the processor would see if all ROM were disabled. Bank switching can \ j
be accomplished in one of two ways. [J
The bank in use is a function of the value stored in the configuration register. A
store to this register will always take effect immediately. An indirect store to this {
register, using programmed bank configuration values, can be accomplished by writing (
to one of the indirect load registers known as LCRs, located in the $FF00 region of ^
memory. By writing to an LCR, the contents of its corresponding PCR (PreConfiguration
Register) will be latched into the configuration register. This allows the programmer to j j
set up four different preprogrammed configurations that allow each bank to be personal- lj
ized ahead of time; e.g., bank 1 as a data bank might be strictly a RAM bank with no
ROM or I/O enabled, while bank 0 as the system bank can have the system ROM and t
I/O enabled by default. Additionally, reading any LCR will return the value of its )
corresponding PCR.
When dealing with 64K banks of memory at once, it may be desirable to bank in
bank 1 but still retain the system RAM (stack, zero page, screen, etc.). The MMU has \ j
provisions for what is referred to as common RAM. This RAM does not bank and is Lj
programmable in size and position (top, bottom, or both) in the memory map. The size
is set by bits 0 and 1 in the RAM Configuration Register (RCR). If the value of the ( j
bits is 0, IK will be common. Values of 1, 2 and 3 produce common areas of 4K, 8K [J
and 16K respectively. If bit 2 of the RCR is set, bottom memory is held common; if bit
3 is set, then top memory is common. In all cases, common RAM is physically located ,
in bank 0. \
Zero page and page one can be located (or relocated) independently of the ^
RCR. When the processor accesses an address that falls within zero page or page
one, the MMU adds to the high-order processor address the contents of the P0 j j
register pair or the PI register pair, respectively, and puts this new address on the I—1
bus, including the extended addressing bit A16. RAM banking will occur as appropriate
to access the new address. Writes to the P0 and PI registers will be stored in pre- \ (
latch until a write to the respective low byte page pointer occurs. This prevents a PxH (J
high byte page pointer from affecting the translated address until both high and low
bytes have been written. Common memory overrides the page pointers. /
At the same time, the contents of the P0 and PI registers are applied to a digital '
comparator, and a reverse substitution occurs if the address from the 8502 falls within
the page pointed to by the register. This results in a swapping of the zero page or page . ,
one with the memory that it replaced. Swapping occurs only if the swapped area is j j
defined as RAM; i.e., system or function ROM must always be at its assigned addresses
and thus should not be back-substituted but of course will not cause contention of any
kind. Note that upon system reset, the pointers are set to true zero page and true page 1 j
one. "—'
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