Commodore 128 Programmer's Reference Manual page 585

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C128 HARDWARE SPECIFICATIONS 575
the C128 system, but some important electrical and timing specifications of the Z80. For
more information on Z80 bus interfacing, consult the Zilog Z80 Data Book.
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SYSTEM DESCRIPTION
pi The Z80A, a 4MHz version of Zilog's standard Z80 processor, is included as an
| alternate processor in the C128 system. This allows the C128 to run the CPM 3.0
operating system at an effective speed of 2 MHz. The Z80 is interfaced to the 8502 bus
interface and can access all the devices that the Z80 can access. The bus interface for the
I I Z80 (the most complex part of the Z80 implementation) is described in this section,
< l along with Z80's operation as a coprocessor in the C128 system.
NOTE: See the Signal Description section later in this chapter for
definitions of the signals mentioned in the following paragraphs.
BUS INTERFACE
Because a Z80 bus cycle is much different than a 65xx family bus cycle, a certain
amount of interfacing is required for a Z80 to control a 65xx-type bus. Since the Z80
has built-in bus arbitration control lines, it is possible to isolate the Z80 by tri-stating its
address lines. Thus, both the Z80 and the 8502 share common address lines.
The interfacing of the data lines is more complex. Because of the shared nature of
the bus during Z80 mode, the Z80 must be isolated from the bus during AEC low. Thus,
a tri-statable buffer must drive the processor bus during Z80 data writes. The reverse
situation occurs during a Z80 read—the Z80 must not read things that are going on
during AEC low; it must latch the data that was present during AEC high. Thus, a
transparent latch drives the data input to the Z80. It is gated by the Z80 read-enable
output, and latched when the 1 MHz clock is low. It will be seen that the Z80 actually
runs during AEC low, but that the data bus interfaces with it only during AEC high.
CONTROL INTERFACE
The Z80 control read-enable interfacing must provide useful clock pulses to the Z80,
and must tailor the Z80 and write-enable signals for the 8502-type bus protocol. The
Z80 clock is provided by the VIC chip, and is basically a 4MHz clock that occurs only
during AEC low, as seen in Figure 16-6. This ensures that the Z80 is clocked only when
it is actively on the bus. One additional consideration in clocking the Z80 is that while
all of the 8502 levels and most of the Z80 levels are TTL-compatible, the Z80 clock
input expects levels very close to 5 volts. For that reason, the output from the VIC chip
is processed by the 9-volt supply; thus, the 9-volt circuit must be operational for the
Z80, and the system, to function. The most common power-up failure for the C128 is a
blown 9-volt fuse.