Commodore 128 Programmer's Reference Manual page 587

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C i 28 HARDWARE SPECIFICATIONS 577
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When the /Z80EN line goes high, it triggers a Z80 /BUSRQ. The Z80 then relin
quishes the bus by pulling /BUSACK low. This action drives the 8502 AEC high and
(providing VIC does not request a DMA) also drives the 8502 RDY line high, enabling
the 8502. To switch back, a low on the Z80 /BUSRQ will result in Z80 /BUSACK
going high, tri-stating and halting the 8502.
See Appendix K on CP/M for interchip communication details.
SIGNAL DESCRIPTION
The list below defines each Z80 signal. The Z80 pin configuration is shown in Figure 16-7.
Address Bus (Ao-Al5): 16-bit tri-stating address bus. Used for 16-bit I/O cycles. This
allows up to 256 input or 256 output ports. During refresh time, the lower 7 bits
contain a valid refresh address. (This signal is not used in the C128 system.)
Data Bus (D<r-D7): Input/output bus capable of tri-stating; used for 8-bit exchanges
with memory and I/O devices.
Machine Cycle One (/M,): Output, active low. This signal indicates that the current
machine cycle is the operation code fetch of an instruction execution. During
execution of a two-byte opcode, M{ is generated, as each byte is fetched. Mx also
occurs with an input/output request (/IORQ) to indicate an interrupt acknowledge
cycle. The Mi line is used to disable the I/O decoder during an interrupt acknowl
edge cycle (See Input/Output Request).
Memory Request (/MREQ): Active low, tri-state output that indicates that the address
bus holds a valid address for a memory read or write operation.
Input/Output Request (/INRQ): Active low, tri-state output. The /INRQ signal
indicates that the lower half of the address bus holds a valid address for an I/O
read or write operation. An /INRQ signal is also generated with a Mx signal when
an interrupt is being acknowledged to indicate that an interrupt response vector
can be placed on the data bus. An interrupt can acknowledge during /Mi; I/O
operations never occur during /Mi.
Memory Read (/RD): Active low, tri-state output. /RD indicates that the CPU wants
to read data from memory or from an I/O device. This signal is generally used to
gate-read data onto the data bus.
Memory Write (/WR): Active low tri-state output. AVR indicates that the data bus
holds valid data to be processed by memory or by an I/O device.
Refresh (/RFSH): Active low output used to indicate that the address bus holds a
refresh address in its lower 7 bits. Thus, the current /MREQ signal should be used
to do a refresh read to all dynamic memories not refreshed from an alternate source.
A7 is set to 0 and the upper 8 bits contain the I register at this time.
Halt State (/HALT): Active low output, indicating that the Z80 has executed a halt
instruction and is awaiting some kind of interrupt before execution can continue.
While in the halt state, the Z80 continuously executes NOPs to continue refresh
activity.
Wait (/WAIT): Active low input, used to drive the Z80 into wait states. As long as this
signal is low, the Z80 executes wait states; thus, this signal can be used to access
slow memory and I/O devices.