Commodore 128 Programmer's Reference Manual page 475

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_^_ THE COMMODORE 128 OPERATING SYSTEM 465
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set pnor to switching out I/O in order for them to be of any service. Note that BASIC uses
the PCRs; if you alter them while BASIC is resident, you may obtain unpredictable results.
pi The MMU registers control the memory organization for RAM, BASIC, Kernal
I i and character ROM, internal and external function ROM, and I/O. The MMU has
additional registers that determine the mode (C128, C64 or CP/M) in which the
pj Commodore 128 operates, the common RAM configurations, and the location of pages
j j 0 and 1. The registers in the MMU that control these operations are the Mode
Configuration Register (MCR), the RAM Configuration Register (RCR), and the
^ Page Pointers respectively. The following sections explain how these additional regis-
j | ters of the Memory Management Unit operate.
THE MODE CONFIGURATION REGISTER
| I The Mode Configuration Register (MCR) specifies which microprocessor is currently in
operation (8502, Z80A) and which operating system mode is currently invoked (C128 or
p C64). The MCR is located at address $D505. As in the other registers in the MMU,
j | each bit in the Mode Configuration Register controls a separate and independent
1 operation.
RBit 0 determines which microprocessor is in control of the Commodore 128. Bit 0 is
powered-up low so the Z80 microprocessor initiates control of the computer. The Z80
performs a small start-up procedure, then bit 0 is set to a 1 and the 8502 takes over
if no CP/M system disk is present in the disk drive.
r~> When the Commodore 128 is first powered-up or reset and the disk drive detects
{ | the CP/M operating system diskette in the drive, the Z80A microprocessor BOOTs the
CP/M operating system from disk. The value of bit 0 in the Mode Configuration
Register in this case is 0. When the Z80A takes control of the Commodore 128, all
H memory references from $0000 through $0FFF are translated to $D000 through $DFFF,
i I where the CP/M BIOS exists in ROM. For memory accesses in the range $0000 through
$0FFF in the Z80 BIOS, the memory status lines MS0 and MSI are brought low to
p reflect ROM; otherwise they are high. Note that C64 mode and Z80A mode is an
I undefined configuration.
Bits 1 and 2 are not used. They are reserved for future expansion. IF0, bit 3 sets
an input for FAST serial. It is not used as an input port at all.
j | Bit 3 is the fast serial (FSDIR) disk drive control bit. It acts like a bit in a
I \ bidirectional 6529 port, which means it acts differently depending upon whether the bit
is used for input or output operation. As an output signal, bit 3 controls the direction of
<-* the data in the disk drive data buffer. The MMU pin FSDIR reflects the status of bit 3,
j | which is reset to zero upon power-up. If bit 3 is equal to 1, an output operation occurs;
' * selecting a data direction for the data in the serial bus buffer. If zero, bit 3 sets
an input for FAST serial. It is not used as an input port at all.
f"* Bits 4 and 5 are the /GAME and /EXROM sense bits respectively. These cartridge
I control lines initiate Commodore 64 mode and act as the /GAME and /EXROM
hardware lines as in the Commodore 64. When these control lines detect a cartridge in
^ the Commodore 128 expansion port, C64 mode is instantly enabled, the computer acts
' ; ! as a Commodore 64 and takes its instructions from the software built into the cartridge.
1 Upon power-up, /GAME and /EXROM are pulled as inputs. If either one is low, C64