Commodore 128 Programmer's Reference Manual page 581

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C128 HARDWARE SPECIFICATIONS 571
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RESET—This input is used to reset or start the processor from a power down
condition. During the time that this line is held low, writing to or from the
processor is inhibited. When a positive edge is detected on the input, the
processor will immediately begin the reset sequence. After a system initialization
time of 6 cycles, the mask interrupt flag will be set and the processor will load the
program counter from the contents of memory locations $FFFC and $FFFD. This is
the start location for program control. After Vcc reaches 4.75 volts in a power up
routine, reset must be held low for at least 2 cycles. At this time the R/W line will
become valid.
INTERRUPT REQUEST (IRQ)—TTL input; requests that the processor initiate an
interrupt sequence. The processor will complete execution of the current instruc
tion before recognizing the request. At that time, the interrupt mask in the Status
Code Register will be examined. If the interrupt mask is not set, the processor will
begin an interrupt sequence. The Program Counter and the Processor Status
Register will be stored on the stack and the interrupt disable flag is set so that no
other interrupts can occur. The processor will then load the program counter from
the memory locations $FFFE and $FFFF.
NON-MASKABLE INTERRUPT REQUEST (NMI)—TTL input, negative edge
sensitive request that the processor initiate an interrupt sequence. The processor
will complete execution of the current instruction before recognizing the request.
The Program Counter and the Processor Status Register will be stored on the
stack. The processor will then load the program counter from the memory
locations $FFFA and $FFFB. Since NMI is non-maskable, care must be taken to
insure that the NMI request will not result in system fatality.
ADDRESS ENABLE CONTROL (AEC)—The Address Bus is only valid when the
AEC line is high. When low, the address bus is in a high impedance state. This
allows DMA's for dual processor systems.
I/O PORT (Po-P6)—Bidirectional port used for transferring data to and from the
processor directly. The Data Register is located at location $0001 and the Data
Direction Register is located at location $0000.
R/W—TTL level output from processor to control the direction of data transfer between
the processor and memory, peripherals, etc. This line is high for reading memory
and low for writing.
RDY—Ready. TTL level input, used to DMA the 8502. The processor operates
normally while RDY is high. When RDY makes a transition to the low state, the
processor will finish the operation it is on, and any subsequent operation if it
is a write cycle. On the next occurrence of read cycle the processor will halt,
making it possible to gain complete access to the system bus.
PROCESSOR TIMING
This section explores the timing considerations of the 8502 processor unit. Table 16-5 is-
a processor timing chart. Figure 16-4 presents timing diagrams that show both general
timing and the particular method of clock stretching used in 2 MHz mode.