Commodore 128 Programmer's Reference Manual page 632

622 COMMODORE 128
mask bit written with a one will be cleared, while those mask bits written with a 0
will be unaffected. If bit 7 of the data written is a ONE, any mask bit written with a one
will be set, while those mask bits written with a 0 will be unaffected. In order for an
interrupt flag to set IR and generate an Interrupt Request, the corresponding MASK bit
must be set.
READ (INT DATA)
REG NAME
D ICR IR 0 0 FLG SP ALRM TB TA
WRITE (INT MASK)
REG NAME
D ICR S/C X X FLG SP ALRM TB TA
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CONTROL REGISTERS
There are two control registers in the 6526, CRA and CRB. CRA is associated
with TIMER A and CRB is associated with TIMER B. The register format is as
follows:
u
u
CRA:
u
BIT NAME FUNCTION
0 START 1 = START TIMER A, 0 = STOP TIMER A, This bit is automat
ically reset when underflow occurs during one-shot mode.
1 PBON 1 = TIMER A output appears on PB6, 0 = PB6 normal operation.
2 OUTMODE 1 = TOGGLE, 0 = PULSE
3 RUNMODE 1 = ONE-SHOT, 0 = CONTINUOUS
4 LOAD 1 = FORCE LOAD (this is a STROBE input, there is no data
storage, bit 4 will always read back a 0 and writing a 0 has no
effect).
5 INMODE 1 = TIMER A counts positive CNT transitions, 0=TIMER A counts
<\>2 pulses.
6 SPMODE 1 = SERIAL PORT output (CNT sources shift clock), 0 = SERIAL
PORT input (external shift clock required).
7 TODIN 1 = 50 Hz clock required on TOD pin for accurate time, 0=60 Hz
clock required on TOD pin for accurate time.
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