BONFIGLIOLI Act 201 Operating Instructions Manual page 157

Parameter
E1: data input D; E2: clock input C; Q: output
If logic "0" is present at input 2 (clock input C), the previous logic state is maintained
at the output independent of the status of input 1 (data input D).
If a positive clock edge is received at clock pulse input C, the signal present at data
input D is transmitted to the output. The output maintains its state Q
positive clock edge is received.
If a negative clock edge is received, the output signal remains unchanged.
06/07
06/07
Operation Mode Logic
E1; D
E2; C
E2; C
E1; D
Q
Operating Instructions ACTIVE
Operating Instructions ACTIVE
D Flip-Flop
= 30
E1
Q
D
Q
0 0 Q
n-1
1 0 Q
n-1
0 0–>1 0
1 0–>1
1
Status
hold
hold
sample
sample
until the next
n-1
155
155