Roms And Registers; Safe Loading To Parameter Ram And Target/Slew Ram - Analog Devices ADAV4601 System Design Document

2. The filter coefficients will have to be safe loaded. See the Safe Loading to Parameter RAM and Target/Slew
RAM section for more details. Move the coefficient value into the safeload parameter registers.
3. Move the addresses of the respective filter coefficients into the safeload addresses registers.
4. Initiate the safe load by setting Bit 4 in Register 0x0200 to 1.

ROMS and Registers

When the ADAV4601 is configured for use with a custom flow it contains two ROMS: program and parameter. Both
can be stored externally on an EEPROM and can be loaded after power-up.
Program ROM
Program ROM is 42-bits wide and occupies Address 0x1400 to Address 0x1FFF. This is where the audio flow
generated in SigmaStudio is stored.
Parameter ROM
Parameter ROM is 28-bits wide and occupies Address 0x1000 to Address 0x13FF. Default parameters for default
flow and custom flow are stored here.

Safe Loading to Parameter RAM and Target/Slew RAM

Up to five safe load registers can be loaded with parameter RAM address data. The data is transferred to the
requested address when the RAM is idle. It is recommended to use this method for dynamic updates during run
time. For example, a complete update of one biquad section can occur in one audio frame. This method is not
available for writing to the program RAM or control registers.
There are ten safe load registers operating in pairs of five, where five of them store addresses and five of them store
data. To safe load a register, move its address into a safe load address register and move its data into the
corresponding safe load data register. If it is a parameter RAM, set Bit 4 in Register 0x0200 to 1 to initiate the safe
load. If it is a target/slew RAM, set Bit 5 in Register 0x0200 to 1 to initiate the safe load.
The safe load data registers are located from Address 0x2040 to Address 0x2044 and are five-bytes wide.
The safe load address registers are located from Address 0x2045 to Address 0x2049 and are two-bytes wide.
The last five instructions of the program RAM are used for the safe load process; therefore, the program length
should be limited to 2555 cycles (2560 − 5). It is guaranteed that the safe load occurs within one LRCLK period (21
µs at f = 48 kHz) of the initiate safe transfer bit being set. Safe load only updates those safe load registers that have
S
been loaded with new data since the last safe load operation. For example, if only two parameters or target RAM
locations are updated, it is only necessary to load two of the safe load registers; the other safe load registers are
ignored because they contain old data.
ADAV4601 System Design Document
Rev.1 August 2009
34 2040 0001FF57
34 2041 0003FEAE
34 2042 0001FF57
34 2043 00E27D65
34 2044 0F95853E
34 2045 0001
34 2046 0002
34 2047 0003
34 2048 0004
34 2049 0005
34 0200 0010
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