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Analog Devices ADAU186x Manuals
Manuals and User Guides for Analog Devices ADAU186x. We have
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Analog Devices ADAU186x manual available for free PDF download: Hardware Reference Manual
Analog Devices ADAU186x Hardware Reference Manual (337 pages)
Brand:
Analog Devices
| Category:
Motherboard
| Size: 11 MB
Table of Contents
Scope
1
Disclaimer
1
Table of Contents
2
Revision History
9
Using the Adau186X Hardware User Guide
10
Number Notations
10
Register Access Conventions
10
Acronyms and Abbreviations
10
Introdcution to the Adau186X
11
System Clocking and Power-Up
12
Power-Up/Power-Down Operation and Options
12
DVDD LDO Regulator
13
HPLDO Regulator
13
Clock Initialization
13
Pll
15
Frequency Multiplier
15
Transition between PLL, Frequency Multiplier, and Bypass
15
Multichip Phase Syncronization
16
Clock Output
16
Power Supply Sequencing
16
Signal Routing
17
Input Signal Paths
18
Analog Inputs
18
Digital Microphone Inputs
20
Analog-To-Digital Converters
20
Output Signal Paths
22
Analog Outputs
22
Digital-To-Analog Converters
23
PDM Outputs
23
Asynchronous Sample Rate Converters
24
Interpolation and Decimation Blocks
24
Signal Levels
24
Equalizer (EQ)
25
Power and Run Control
25
EQ Clear
25
Read/Write Data Formats
25
Memory Address Allocation
25
Parameter Bank Switching
25
Parameter Memory Access
25
Fastdsp Core
26
Instructions
26
Filter Precision
26
Flags and Conditional Execution
26
Input Sources
26
Power and Run Control
26
Data Memory
27
Parameters
27
Parameter Bank Switching
27
Parameter Bank Copying
27
Parameter Memory Access
27
Fastdsp Parameter Safeload
28
Digital Turbo Mode
29
Normal Mode
29
TURBO Mode
29
Tensilica DSP
30
Dma
30
Fifo
30
Data Sync
30
Uart
30
Qspi
30
Watchdog
30
General-Purpose Timer
30
Interrupt
30
Debug Interface
30
Memory Mapping
31
Power Saving Options
32
ADC Bias Current Control
32
Control Port
34
Burst Mode Communication
34
Reading and Writing to Memories
35
I 2 C Control Port
35
SPI Control Port
38
UART Control Port
39
Self Boot
41
Multipurpose Pins
42
Serial Data Ports
43
Applications Information
45
Power Supply Bypass Capacitors
45
Layout
45
Grounding
45
Instance Table: Adau186X
46
Register Summary: DMA
47
Register Details: DMA
48
DMA Status Register
48
DMA Configuration Register
48
DMA Channel Primary Control Data Base Pointer Register48
48
DMA Channel Alternate Control Data Base Pointer Register
48
DMA Channel Software Request Register
48
DMA Channel Request Mask Set Register
49
DMA Channel Request Mask Clear Register
50
DMA Channel Enable Set Register
50
DMA Channel Enable Clear Register
51
DMA Channel Primary-Alternate Set Register
51
DMA Channel Primary-Alternate Clear Register
51
DMA Channel Priority Set Register
52
DMA Channel Priority Clear Register
53
DMA Interrupt Enable Set Register
53
DMA Interrupt Enable Clear Register
54
DMA Interrupt Status Clear Register
54
DMA Per Channel Error Clear Register
55
DMA Per Channel Invalid Descriptor Clear Register
55
DMA Channel Bytes Swap Enable Set Register
56
DMA Channel Bytes Swap Enable Clear Register
56
DMA Channel Source Address Decrement Enable Set Register
57
DMA Channel Source Address Decrement Enable Clear Register
57
DMA Channel Destination Address Decrement Enable Set Register
58
DMA Channel Destination Address Decrement Enable Clear Register
58
DMA Controller Revision ID Register
58
Register Summary: Serial Peripheral Interface QSPI
59
Register Details: Serial Peripheral Interface
60
Control Register
60
Receive Control Register
64
Transmit Control Register
66
Clock Rate Register
67
Delay Register
67
Slave Select Register
68
Received Word Count Register
70
Received Word Count Reload Register
70
Transmitted Word Count Register
70
Transmitted Word Count Reload Register
71
Interrupt Mask Register
71
Interrupt Mask Clear Register
72
Interrupt Mask Set Register
72
Status Register
73
Masked Interrupt Condition Register
75
Masked Interrupt Clear Register
76
Receive FIFO Data Register
77
Transmit FIFO Data Register
77
Memory Mapped Read Header Register
78
SPI Memory Top Address Register
80
Register Summary: Tensilica DSP (SOC)
81
Register Details: Tensilica DSP (SOC)
82
SOC Clock Enable Register
82
SOC Dummy Register 1
82
SOC Dummy Register 2
82
SOC Dummy Register 3
82
SOC Low Priority Level Trigger Interrupt Connection Register
83
SOC High Priority Level Trigger Interrupt Connection Register
83
SOC Low Priority Edge Trigger Interrupt Connection Register
84
SOC High Priority Edge Trigger Interrupt Connection Register
85
SOC Error Status Register
85
SOC Pfault Information Register
85
SOC Memory Light-Sleep Register
86
Register Summary: Universal Asynchronous Receiver/Transmitter
87
Register Details: Universal Asynchronous Receiver/Transmitter
88
Receive/Transfer Buffer Register
88
Interrupt Enable Register
88
Interrupt ID Register
88
Line Control Register
89
Modem Control Register
90
Line Status Register
90
Modem Status Register
91
Scratch Buffer Register
92
FIFO Control Register
92
Fractional Baud Rate Register
93
Baudrate Divider Register
93
Second Line Control Register
93
UART Control Register
93
RX FIFO Byte Count Register
94
TX FIFO Byte Count Register
94
RS485 Half-Duplex Control Register
94
Auto Baud Control Register
94
Auto Baud Status (Low) Register
95
Auto Baud Status (High) Register
95
Register Summary: GPT
96
Register Details: GPT
97
16-Bit Load Value Register
97
16-Bit Current Timer Value Register
97
Control Register
97
Clear Interrupt Register
98
Status Register
98
Register Summary: Watchdog Timer Register Map WDT
99
Register Details: Watchdog Timer
100
Watchdog Timer Load Value Register
100
Current Count Value Register
100
Watchdog Timer Control Register
100
Refresh Watchdog Register
101
Timer Status Register
101
Minimum Load Value Register
101
Register Summary: Audio Data Path
102
Register Details: Audio Data Path
110
ADI Vendor ID Register
110
Device ID Register
110
Revision Code Register
110
ADC, DAC, Headphone Power Controls Register
110
PLL and PGA Power Controls Register
111
Digital MIC Power Controls Register
111
Serial Port, PDM Output, and DMIC CLK Power Controls Register
112
DSP Power Controls Register
113
ASRC Power Controls Register
113
Interpolator Power Controls Register
114
Decimator Power Controls Register
114
State Retention Controls Register
115
Retention Control for ADP and SOC Memories Register
115
Chip Power Control Register
115
Clock Control Register
116
PLL Input Divider Register
116
PLL Feedback Integer Divider (Lsbs) Register
117
PLL Feedback Integer Divider (Msbs) Register
117
PLL Fractional Numerator Value (Lsbs) Register
117
PLL Fractional Numerator Value (Msbs) Register
117
PLL Fractional Denominator (Lsbs) Register
117
PLL Fractional Denominator (Msbs) Register
117
PLL Update Register
118
TDSP Clock Rate, BUS(AHB/APB) Clock Rate and FFSRAM2 Rate Register
118
AON and UART_CTRL Clock Rate Register
119
Frequency Multiplier Enable, Ratio Register
119
PLL Frequency Index and ADC Frequency Index Register
119
ADP_CLOCK_ENABLE, Low Byte Register
120
ADP_CLOCK_ENABLE, High Byte Register
120
ADC Sample Rate Control Register
120
ADC IBIAS Controls Register
121
ADC HPF Control Register
122
ADC Mute and Compensation Control Register
122
Analog Input Precharge Time Register
123
ADC Channel Mutes Register
124
ADC Channel 0 Volume Control Register
124
ADC Channel 1 Volume Control Register
124
ADC Channel 2 Volume Control Register
125
ADC Dithering Level Register
125
PGA Channel 0 Gain Control Lsbs, Mute, Boost, Slew Register
125
PGA Channel 0 Gain Control Msbs Register
126
PGA Channel 1 Gain Control Lsbs, Mute, Boost, Slew Register
126
PGA Channel 1 Gain Control Msbs Register
126
PGA Channel 2 Gain Control Lsbs, Mute, Boost, Slew Register
127
PGA Channel 2 Gain Control Msbs Register
127
PGA Slew Rate and Gain Link Register
127
PGA RIN and Power Mode Register
128
DMIC Clock Rate Control Register
128
DMIC Channel 0 and Channel 1 Rate, Order, Mapping, and Edge Control Register
129
DMIC Channel 2 and Channel 3 Rate, Order, Mapping, and Edge Control Register
129
DMIC Volume Options Register
130
DMIC Channel Mute Controls Register
130
DMIC Channel 0 Volume Control Register
131
DMIC Channel 1 Volume Control Register
131
DMIC Channel 2 Volume Control Register
132
DMIC Channel 3 Volume Control Register
132
DMIC Channel 4 and Channel 5 Rate, Order, Mapping, and Edge Control Register
132
DMIC Channel 6 and Channel 7 Rate, Order, Mapping, and Edge Control Register
133
DMIC Clock Map, DMIC Clock 1 Source Pin Select Register
134
DMIC Channel 4 Volume Control Register
134
DMIC Channel 5 Volume Control Register
135
DMIC Channel 6 Volume Control Register
135
DMIC Channel 7 Volume Control Register
135
DAC Sample Rate, Filtering, and Power Controls Register
136
DAC Volume Lunk, HPF, and Mute Controls Register
136
DAC Channel 0 Volume Register
137
DAC Channel 0 Routing Register
137
Headphone Control Register
139
HP Low Voltage Mode Enable, CM Enable Register
139
HP Low Voltage Auto Switch Mode, Delay, CM Delay Register
140
HP Low Voltage Auto Switch (Go) Register
140
HPLDO CTRL Register
141
Analog Backend Power Control
141
Memory Power Control Register
141
CM Control Register
142
IRQ Wakeup Control Register
142
DLDO Control Register
143
Fast to Slow Decimator Sample Rates Channel 0 and Channel 1 Register
143
Fast to Slow Decimator Sample Rates Channel 2 and Channel 3 Register
143
Fast to Slow Decimator Sample Rates Channel 4 and Channel 5 Register
144
Fast to Slow Decimator Sample Rates Channel 6 and Channel 7 Register
144
Fast to Slow Decimator Channel 0 Input Routing Register
145
Fast to Slow Decimator Channel 1 Input Routing Register
146
Fast to Slow Decimator Channel 2 Input Routing Register
147
Fast to Slow Decimator Channel 3 Input Routing Register
148
Fast to Slow Decimator Channel 4 Input Routing Register
149
Fast to Slow Decimator Channel 5 Input Routing Register
150
Fast to Slow Decimator Channel 6 Input Routing Register
152
Fast to Slow Decimator Channel 7 Input Routing Register
153
Slow to Fast Interpolator Sample Rates Channel 0/Channel 1 Register
154
Slow to Fast Interpolator Sample Rates Channel 2/Channel 3 Register
154
Slow to Fast Interpolator Sample Rates Channel 4/Channel 5 Register
155
Slow to Fast Interpolator Sample Rates Channel 6/Channel 7 Register
155
Slow to Fast Interpolator Channel 0 Input Routing Register
156
Slow to Fast Interpolator Channel 1 Input Routing Register
158
Slow to Fast Interpolator Channel 2 Input Routing Register
159
Slow to Fast Interpolator Channel 3 Input Routing Register
161
Slow to Fast Interpolator Channel 4 Input Routing Register
163
Slow to Fast Interpolator Channel 5 Input Routing Register
165
Slow to Fast Interpolator Channel 6 Input Routing Register
166
Slow to Fast Interpolator Channel 7 Input Routing Register
168
Input ASRC Control, Source, and Rate Selection Register
170
Input ASRC Channel 0 and Channel 1 Input Routing Register
170
Input ASRC Channel 2 and Channel 3 Input Routing Register
171
Output ASRC Control Register
172
Output ASRC Channel 0 Input Routing Register
173
Output ASRC Channel 1 Input Routing Register
174
Output ASRC Channel 2 Input Routing Register
175
Output ASRC Channel 3 Input Routing Register
176
Fastdsp Run Register
177
Fastdsp Current Bank and Bank Ramping Controls Register
178
Fastdsp Bank Ramping Stop Point Register
179
Fastdsp Bank Copying Register
179
Fastdsp Frame Rate Source Register
180
Fastdsp Fixed Rate Division Msbs Register
180
Fastdsp Fixed Rate Division Lsbs Register
180
Fastdsp Modulo N Counter for Lower Rate Conditional Execution Register
181
Fastdsp Generic Conditional Execution Registers
181
Fast DSP Safeload Address Register
182
Fastdsp Safeload Parameter 0 Value Register
182
Fastdsp Safeload Parameter 1 Value Register
182
Fastdsp Safeload Parameter 1 Value Register
183
Fastdsp Safeload Parameter 2 Value Register
183
Fastdsp Safeload Parameter 2 Value Register
184
Fastdsp Safeload Parameter 3 Value Register
184
Fastdsp Safeload Parameter 4 Value Register
184
Fastdsp Safeload Parameter 4 Value Register
185
Fastdsp Safeload Update Register
185
Fastdsp Safeload Parameter 0 Value Register
185
Fastdsp Safeload Parameter 0 Value Register
186
EQ Configure Register
186
EQ Routing Register
186
Tensilica DSP Software Reset Register
188
Tensilica DSP Alternative Reset Vector Enable Register
188
Tensilica DSP Alternative Reset Vector Address, Byte 0 Register
188
Tensilica DSP Alternative Reset Vector Address, Byte 1 Register
188
Tensilica DSP Alternative Reset Vector Address, Byte 2 Register
189
Tensilica DSP Alternative Reset Vector Address, Byte 3 Register
189
Tensilica DSP Run Register
189
Serial Port 0 Control 1 Register
189
Serial Port 0 Control 2 Register
190
Serial Port 0 Output Routing Slot 0 (Left) Register
190
Serial Port 0 Output Routing Slot 1 (Right) Register
192
Serial Port 0 Output Routing Slot 2 Register
193
Serial Port 0 Output Routing Slot 3 Register
194
Serial Port 0 Output Routing Slot 4 Register
196
Serial Port 0 Output Routing Slot 5 Register
197
Serial Port 0 Output Routing Slot 6 Register
198
Serial Port 0 Output Routing Slot 7 Register
200
Serial Port 0 Output Routing Slot 8 Register
201
Serial Port 0 Output Routing Slot 9 Register
202
Serial Port 0 Output Routing Slot 10 Register
204
Serial Port 0 Output Routing Slot 11 Register
205
Serial Port 0 Output Routing Slot 12 Register
206
Serial Port 0 Output Routing Slot 13 Register
208
Serial Port 0 Output Routing Slot 14 Register
209
Serial Port 0 Output Routing Slot 15 Register
210
Serial Port 1 Control 1 Register
212
Serial Port 1 Control 2 Register
212
Serial Port 1 Control 2 Register
213
Serial Port 1 Output Routing Slot 0 (Left) Register
213
Serial Port 1 Output Routing Slot 1 (Right) Register
214
Serial Port 1 Output Routing Slot 2 Register
216
Serial Port 1 Output Routing Slot 3 Register
217
Serial Port 1 Output Routing Slot 4 Register
218
Serial Port 1 Output Routing Slot 5 Register
220
Serial Port 1 Output Routing Slot 6 Register
221
Serial Port 1 Output Routing Slot 7 Register
222
Serial Port 1 Output Routing Slot 8 Register
224
Serial Port 1 Output Routing Slot 9 Register
225
Serial Port 1 Output Routing Slot 10 Register
226
Serial Port 1 Output Routing Slot 11 Register
228
Serial Port 1 Output Routing Slot 12 Register
229
Serial Port 1 Output Routing Slot 13 Register
230
Serial Port 1 Output Routing Slot 14 Register
232
Serial Port 1 Output Routing Slot 15 Register
233
PDM Sample Rate and Filtering Control Register
234
PDM Muting, High-Pass, and Volume Options Register
235
PDM Output Channel 0 Volume Register
235
PDM Output Channel 1 Volume Register
236
PDM Output Channel 0 Routing Register
236
PDM Output Channel 1 Routing Register
238
Multipurpose Pin 0/Pin 1 Mode Select Register
240
Multipurpose Pin 2/Pin 3 Mode Select Register
241
Multipurpose Pin 4/Pin 5 Mode Select Register
241
Multipurpose Pin 6/Pin 7 Mode Select Register
242
Multipurpose Pin 8/Pin 9 Mode Select Register
243
Multipurpose Pin 10/Pin 11 Mode Select Register
244
Multipurpose Pin 12/Pin 13 Mode Select Register
244
Multipurpose Pin 14/Pin 15 Mode Select Register
245
Multipurpose Pin 16/Pin 17 Mode Select Register
246
Multipurpose Pin 18/Pin 19 Mode Select Register
247
Multipurpose Pin 20/Pin 21 Mode Select Register
247
Multipurpose Pin 22/Pin 23 Mode Select Register
248
Multipurpose Pin 24/Pin 25 Mode Select Register
249
General-Purpose Input Debounce Control and IRQ Input Debounce Control Register
250
MCLKO Rate Selection Register
250
General-Purpose Outputs Control Pin 0 to Pin 7 Register
251
General-Purpose Outputs Control Pin 8 to Pin 15 Register
251
General-Purpose Outputs Control Pin 16 to Pin 23 Register
252
General-Purpose Outputs Control Pin 24 to Pin 25 Register
252
DMIC_CLK Pin Controls Register
253
DMIC01 Pin Controls Register
253
DMIC23 Pin Controls Register
254
BCLK_0 Pin Controls Register
254
FSYNC_0 Pin Controls Register
255
SDATAO_0 Pin Control Register
255
SDATAI_0 Pin Controls Register
256
BCLK_1 Pin Controls Register
256
FSYNC_1 Pin Controls Register
257
SDATAO_1 Pin Controls Register
257
SDATAI_1 Pin Controls Register
258
QSPIM_CLK Pin Controls Register
258
QSPIM_CS Pin Controls Register
259
QSPIM_SDIO0 Pin Controls Register
259
QSPIM_SDIO1 Pin Controls Register
260
QSPIM_SDIO2 Pin Controls Register
260
QSPIM_SDIO3 Pin Controls Register
261
UART_COMM_TX Pin Controls Register
261
UART_COMM_TX Pin Controls Register
262
SELFBOOT Pin Controls Register
262
SELFBOOT Pin Controls Register
263
SELFBOOT Pin Controls Register
264
SELFBOOT Pin Controls Register
265
SDA/MISO Pin Controls Register
266
IRQ Signaling and Clearing Register
266
IRQ1 Masking Register
267
IRQ1 Masking Register
268
IRQ1 Masking Register
269
IRQ2 Masking Register
269
IRQ2 Masking Register
270
IRQ2 Masking Register
271
IRQ2 Masking Register
272
IRQ3 Masking Register
272
IRQ3 Masking Register
273
IRQ3 Masking Register
274
IRQ4 Masking Register
275
IRQ4 Masking Register
276
IRQ4 Masking Register
277
Software Interrupts Which Can be Set by the External Host or TDSP Register
278
MP IRQ Clearing Register
278
MP IRQ1 Masking Register
279
MP IRQ1 Masking Register
280
MP IRQ1 Masking Register
281
Fastdsp Working Mode Register
281
Chip Resets Register
281
Fastdsp Current Lambda Register
282
Chip Status 1 Register
282
Chip Status 2 Register
283
Tensilica DSP Self-Boot Indicator Register
283
EQ Status Register
283
Fastdsp ONZ Status Register
284
Power Mode Status, DLDO Scale Busy, CM Delay Counter Done Register
284
Memory Retention Status Register
284
ADP Memory Shutdown Status Register
285
SOC Memory Shutdown Status Register
285
TDSP Mode Status Register
285
TDSP Exception/Error Status Register
285
TDSP Fault Information Register
285
TDSP Fault Information Register
286
TDSP General Purpose Output Bit 0 to Bit 7 Register
286
TDSP General Purpose Output Bit 8 to Bit 15 Register
286
TDSP General Purpose Output Bit 16 to Bit 23 Register
286
TDSP General Purpose Output Bit 24 to Bit 31 Register
287
IRQ1 Status 1 Register
287
IRQ1 Status 2 Register
287
IRQ1 Status 3 Register
288
IRQ1 Status 4 Register
288
IRQ1 Status 5 Register
289
IRQ2 Status 1 Register
289
IRQ2 Status 2 Register
290
IRQ2 Status 3 Register
291
IRQ2 Status 4 Register
291
IRQ2 Status 5 Register
292
IRQ3 Status 1 Register
292
IRQ3 Status 2 Register
293
IRQ3 Status 3 Register
293
IRQ3 Status 4 Register
294
IRQ3 Status 5 Register
294
IRQ4 Status 1 Register
295
IRQ4 Status 2 Register
295
IRQ4 Status 3 Register
296
IRQ4 Status 4 Register
296
IRQ4 Status 5 Register
297
Multipurpose IRQ1 Status 1 Register
297
Multipurpose IRQ1 Status 2 Register
297
Multipurpose IRQ1 Status 3 Register
298
Multipurpose IRQ2 Status 1 Register
298
Multipurpose IRQ2 Status 2 Register
298
Multipurpose IRQ2 Status 3 Register
298
Multipurpose IRQ3 Status 1 Register
299
Multipurpose IRQ3 Status 2 Register
299
Multipurpose IRQ3 Status 3 Register
299
Multipurpose IRQ1 Status 3 Register
299
General-Purpose Input Read 0 to 7 Register
299
General-Purpose Input Read 8 to 15 Register
300
General-Purpose Input Read 16 to 20 Register
301
Control Port Mode Register
302
DAC Noise Control 2 Register
302
DAC Noise Control 1 Register
302
Register Summary: FIFOSRAM0_CONFIGURATION
303
Register Details: FIFOSRAM0_CONFIGURATION
304
Register Summary: FIFOSRAM1_CONFIGURATION
310
Register Details: FIFOSRAM1_CONFIGURATION
311
Register Summary: FIFOSRAM2_CONFIGURATION
317
Register Details: FIFOSRAM2_CONFIGURATION
318
Register Summary: Data Transportation between Datapath and TDSP
324
Register Details: Data Transportation between Datapath and TDSP
326
System Block Diagram
337
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