Table 2-2. U_Msr_Pmon_Global_Ctl Register - Field Definitions; Table 2-3. U_Msr_Pmon_Global_Status Register - Field Definitions; Table 2-4. U_Msr_Pmon_Global_Ovf_Ctl Register - Field Definitions - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Table 2-2. U_MSR_PMON_GLOBAL_CTL Register – Field Definitions
Field
frz_all
ig
rst_all
en_all
ig
pmi_core_sel
en
Table 2-3. U_MSR_PMON_GLOBAL_STATUS Register – Field Definitions
Field
cond
pmi
ig
ov_s0
ov_s1
ov_w
ov_u
Table 2-4. U_MSR_PMON_GLOBAL_OVF_CTL Register – Field Definitions
Field
clr_cond
clr_pmi
ig
clr_ov_s0
clr_ov_s1
clr_ov_w
clr_ov_u
U P G
ERIES NCORE ROGRAMMING UIDE
HW
Bits Reset
Val
31 0 Disable uncore counting (by clearing .en_all) if PMI is received from box
with overflowing counter.
30 0 Read zero; writes ignored. (?)
29 0 Reset All Uncore PMON Counters
28 0 Enable All Uncore PMON Counters
27:9 0 Read zero; writes ignored. (?)
8:1 0 PMI Core Select
Ex:
If counter pmi is sent to U-Box for Box with overflowing counter...
00000000 - No PMI sent
00000001 - Send PMI to core 0
10000000 - Send PMI to core 7
11000100 - Send PMI to core 2, 6 & 7
etc.
0 0 Enable U-Box PMON counters
HW
Bits Reset
Val
31 0 Condition Change
30 0 PMI Received from box with overflowing counter.
31:4 0 Read zero; writes ignored. (?)
3 0 Set if overflow is detected from a S-Box 0 PMON register.
2 0 Set if overflow is detected from a S-Box 1 PMON register.
1 0 Set if overflow is detected from a W-Box PMON register.
0 0 Set if overflow is detected from a U-Box PMON register.
HW
Bits Reset
Val
31 0 Clear Condition Change
30 0 Clear PMI Received bit.
29:4 0 Read zero; writes ignored. (?)
3 0 Clear S-Box 0 Overflow
2 0 Clear S-Box 1 Overflow
1 0 Clear W-Box Overflow
0 0 Clear U-Box Overflow
UNCORE PERFORMANCE MONITORING
Description
Description
Description
2-4