Apic Interrupt Routing; Table 9: Pci Interrupt Routing/Sharing - Intel SE7520JR2 Technical Manual

Intel® Server Board SE7520JR2
Both PCI and IRQ types of interrupts are handled by the ICH5-R. The ICH5-R translates these
to the APIC bus. The numbers in the table below indicate the ICH5-R PCI interrupt input pin to
which the associated device interrupt (INTA, INTB, INTC, INTD) is connected. The ICH5-R I/O
APIC exists on the I/O APIC bus with the processors.
Interrupt
Video
IDE RAID
NIC 10/100 (Not used on
SE7520JR2)
SIO
Legacy IDE
Legacy IDE
82546GB #1
82546GB #2
SCSI Controller #1
SCSI Controller #2
FL Riser TCK & TCO
P64-A Slot 1
P64-A Slot 2
P64-A Slot 3
LP Riser
P64-B Slot 1
P64-B Slot 2
P64-B Slot 3
3.4.3.2

APIC Interrupt Routing

For APIC mode, the Server Board SE7520JR2 interrupt architecture incorporates three Intel I/O
APIC devices to manage and broadcast interrupts to local APICs in each processor. The Intel
I/O APICs monitor each interrupt on each PCI device including PCI slots in addition to the ISA
compatibility interrupts IRQ(0-15). When an interrupt occurs, a message corresponding to the
interrupt is sent across a three-wire serial interface to the local APICs. The APIC bus minimizes
interrupt latency time for compatibility interrupt sources. The I/O APICs can also supply greater
than 16 interrupt levels to the processor(s). This APIC bus consists of an APIC clock and two
bidirectional data lines.
Revision 1.0

Table 9: PCI Interrupt Routing/Sharing

INT A
ICH5R_PIRQB
ICH5R_PIRQC
ICH5R_PIRQD
ICH5R_SERIRQ
ICH5R_PIRQ14
ICH5R_PIRQ15
P64A_IRQ6
P64A_IRQ7
P64B_IRQ2
P64B_IRQ1
P64A_IRQ0
P64A_IRQ0
P64A_IRQ3
P64A_IRQ5
P64B_IRQ4
P64B_IRQ4
P64B_IRQ3
P64B_IRQ2
C78844-002
INT B INT C
P64A_IRQ3 P64A_IRQ5
P64A_IRQ3 P64A_IRQ5
P64A_IRQ5 P64A_IRQ4
P64A_IRQ4 P64A_IRQ2
P64B_IRQ3 P64B_IRQ2
P64B_IRQ3 P64B_IRQ2
P64B_IRQ2 P64B_IRQ1
P64B_IRQ1 P64B_IRQ4
Functional Architecture
INT D
P64A_IRQ4
P64A_IRQ4
P64A_IRQ0
P64A_IRQ1
P64B_IRQ1
P64B_IRQ1
P64B_IRQ4
P64B_IRQ3
53