Post Code Checkpoints; Figure 24. Location Of Diagnostic Leds On Baseboard; Table 75: Post Code Checkpoints - Intel SE7520JR2 Technical Manual

Error Reporting and Handling
Result Amber
MSB
Diagnostic LEDs
LSB
6.5.3

POST Code Checkpoints

Diagnostic LED Decoder
Checkpoint G=Green, R=Red, A=Amber
MSB
03 OFF OFF
04 OFF
05 OFF
06 OFF
08 G OFF
C0 R
C1 R
C2 R
C5 R
168
Green
MSB

Figure 24. Location of Diagnostic LEDs on Baseboard

Table 75: POST Code Checkpoints

LSB
Disable NMI, parity, video for EGA, and DMA controllers. Initialize
BIOS, POST, Run-time data area. Initialize BIOS modules on POST
G G
entry and GPNV area. Initialized CMOS as mentioned in the Kernel
Variable "wCMOSFlags."
Check CMOS diagnostic byte to determine if battery power is OK and
CMOS checksum is OK. Verify CMOS checksum manually by reading
storage area. If the CMOS checksum is bad, update CMOS with
power-on default values and clear passwords. Initialize status register
G OFF OFF
A.
Initializes data variables that are based on CMOS setup questions.
Initializes both the 8259 compatible PICs in the system
Initializes the interrupt controlling hardware (generally PIC) and
G OFF G
interrupt vector table.
Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install
the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer
G G OFF
interrupt.
Traps INT1Ch vector to "POSTINT1ChHandlerBlock."
Initializes the CPU. The BAT test is being done on KBC. Program the
OFF OFF keyboard controller command byte is being done after Auto detection
of KB/MS using AMI KB-5.
R OFF OFF Early CPU Init Start -- Disable Cache - Init Local APIC
R OFF G Set up boot strap processor Information
R G OFF Set up boot strap processor for POST
A OFF G Enumerate and set up application processors
Red
Description
C78844-002
Intel® Server Board SE7520JR2
Off
LSB
Back edge of baseboard
Revision 1.0